## Papers:

### Symbolic charge-based MOSFET model

The new generation of compact MOSFET models provides accurate current, charge, capacitance and noise characteristics as numerical outputs of a rather complicated set of internal equations specific to each model. Clearly, numerical circuit simulation is [...]

### Theory and Modeling Techniques used in PSP Model

Gildenblat, G., Jha, A., Klaassen, D.B.M., Li, X., Scholten, A.J., Smit, G.D.J., van Langevelde, R., Wang, H., Wu, W.,

*Pennsylvania State University, US*This paper describes theoretical foundation and details of the new compact modeling techniques used in the advanced surface-potential-based compact MOSFET model PSP, jointly developed by the Pennsylvania State University and Philips Research. Specific topics include [...]

### An Improved MOS Transistor Model with an Integrated Mobility Model

A new and improved MOS I-V model will be presented using a more exact approach to include surface field dependent mobility effects. Mobility degradation effects are included in the basic I-V differential equation as opposed [...]

### Benchmark Tests on Conventional Surface Potential Based Charge-Sheet Models And the Advanced PUNSIM Development

Chan, M., He, J., Huang, R., Niu, X., Song, Y., Wang, Y., Zhang, G., Zhang, X.,

*Peking University, CN*This paper reports the benchmark test results of surface potential solution, inversion charge and channel current calculation, and short-channel effect model of various surface based charge-sheet models and our PUNSIM development to breakthrough the drawbacks [...]

### Accuracy of Surface-Potential-Based Long-Wide-Channel MOS Transistor Compact Models

Frequently asked questions are addressed, “How accurate are the approximate long-and-wide-channel MOS transistors baseline models that have been used to develop the compact models for computer-aided circuit designs?” Three commonly used surface-potential (US=q*PSIS/kT) approximations of [...]

### Advanced Compact MOSFET Model HiSIM2 Based on Surface Potentials with a Minimum Number of Approximation

Ezaki, T., Iizuka, T., Inagaki, R., Kumashiro, S., Machida, K., Mattausch, H.J., Miura-Mattausch, M., Miyake, M., Miyamoto, S., Navarro, D., Ohguro, T., Sadachika, N., Suzuki, G., Taguchi, M., Takeda, Y., Warabino, T.,

*Hiroshima University, JP*The compact model HiSIM2 supports RF-circuit applications with advanced MOSFETs and is a further development of HiSIM1 which has been released since 2001 for public usage. Important features, required for the real applications, are summarized. [...]

### Halo Doping: Physical Effects and Compact Modeling

As the devices are scaled to ultra short channel lengths, pocket or halo implants have been used widely to reduce DIBL and other short channel effects. Although, the use of halo implants helps with control [...]

### Compact Iterative Field Effect Transistor Model

Iñiguez, B., Jackson, W., Shur, M.S., Turin, V., Veksler, D., Ytterdal, T.,

*Rensselaer Polytechnic Institute, US*Compact models for field effect transistors should satisfy two conflicting requirements. On one hand, they should be simple enough and should contain a small number of physics-based parameters to be suitable for parameter extraction. On [...]

### Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling

Chandrasekaran, K., Cheng, M., Chiah, S.B., Chu, S., Hsia, L.-C., Lim, G.H., Mani Pandey, S., Rustagi, S., See, G.H., Shangguan, W., Zhou, X., Zhu, Z.,

*Nanyang Technological University, SG*In this paper, we extend our unified regional approach to bulk-MOS charge modeling with non-pinned surface potential for various device structures such as PD/FD/UTB SOI and s-DG MOSFETs, including strained-Si channel. The regional solutions make [...]

### BSIM4 and BSIM Multi-Gate Progress

Compact models form an integral part of any circuit design environment, ranging from analog and digital design to mixed-signal design worlds. The models need to be developed and improved in parallel with technology advancements to [...]

### Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques

In nanoscale double gate MOSFETs, the dependence on the bias voltages of the 2D electron barrier topology in the conducting channel is all-important for the operation of the device. We consider a DG MOSFET with [...]

### Recent Upgrades and Applications of UFDG

Recent upgrades of UFDG, a process/physics-based compact model for nonclassical MOSFETs having ultra-thin Si bodies (UTB), are overviewed, and several recent applications of the model are presented, exemplifying the potential benefits of FinFETs in nanoscale [...]

### DC to RF Small-Signal Compact DG MOSFET model

Cerdeira, A., Fjeldly, T.A., Iñiguez, B., Lázaro, A., Moldovan, O.,

*Universitat rovira i Virgili (URV), ES*In this paper we present a complete compact model for doped DG MOSFETs which includes explicit expressions of the channel current and of all small- and large-signal parameters. The model is based on a unified [...]

### An Explicit Quasi-Static Charge-Based Compact Model for Symmetric DG MOSFET

This paper presents a closed-form compact model for the undoped double-gate (DG) MOSFET under symmetrical operation. This charge-based model aims at giving a comprehensive understanding of the device from the circuit design point of view. [...]

### On the Modeling of the Current-Voltage Characteristics of a Symmetrical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with an Undoped Body

Three general classes of solutions are needed to model an arbitrary double-gate (DG) metal-oxide-semiconductor (MOS) capacitor with arbitrary bias conditions. The “zero-field” (F0) and the “zero-potential” (P0) solution regimes are separated by the “zero-field and [...]

### Device Correlation: Modeling using Uncorrelated Parameters, Characterization Using Ratios and Differences

Partial correlations between parameters of different types of devices, such as effective channel lengthfor PMOS and NMOS devices, are often modeled and simulated statistically via correlation coefficients.However this is cumbersome and inefficient from a modeling [...]

### Modeling Small MOSFETs using Ensemble Devices

This paper discribes methodogy to correctly model small area MOSFETs including paremeter extraction and centering using multiple parallel devices for accurate measurments. The method includes adjusting the measured data to recover true single finger behavior, [...]

### Effects of Scaling on Modeling of Analog RF MOS Devices

This paper uses advanced TCAD tools—both IMF-based noise modeling and HB-based distortion modeling—to extract parameters of key importance in developing compact models. Additionally, the TCAD-based modeling provides insight into technology constraints that can potentially influence [...]

### High-Voltage LDMOS Compact Modeling

In compact modeling of high-voltage LDMOS devices often a sub-circuit approach is used. While for the channel region a standard compact MOS model (for example BSIM4, MM11 or PSP) is used, the drift region is [...]

### Analog Compact Modeling for a 20-120V HV CMOS Technology

In this paper we discuss state of the art and new developments of analog modeling for HV CMOS technologies. We will give a detailed overview about the full characterization of a 0.35um high voltage process [...]

### Compact Modeling of Spiral Inductors for RF Applications

Recent growth in RF applications has increased the use of spiral inductors and thus demanded a more accurate model for such devices. In this paper, we develop a compact model for spiral inductors with symmetrical [...]

### Development and Design Kit Integration of a Scalable and Statistical High Current Model for Advanced SiGe HBTs

In this invited paper, we present the methodology for advanced SiGe HBT modeling and its integration into BiCMOS design kits. We review various model choices and describe, in detail, the extraction of the High Current [...]

### Charge-storage calculation for Si-based bipolar transistors from device simulation

Various methods for calculating regional charge storage components in bipolar transistors fromdevice simulation results are compared with respect to their usefulness for compact modeling. Themethods are evaluated for Si and SiGe transistors with very different [...]

### Compact Modeling of Short Channel Double-Gate MOSFETs

This talk presents analytical modeling of short-channel effect in double-gate MOSFETs. 2-D Poisson’s eq. is solved as a boundary value problem in subthreshold. 2-D potential distribution and subthreshold currents have been calculated and verified by [...]

### DC and AC Symmetry Tests for MOSFET Models

Symmetry around Vds=0 is a critical requirement forMOSFET models, e.g. as it affects the ability of a model tosimulate accurately distortion for some RF CMOS mixers.The Gummel Symmetry Test is, until now, the standardtest used [...]

### Scalable MOSFET Short-channel Charge Model in All Regions

Chandrasekaran, K., Cheng, M., Chiah, S.B., Chu, S., Hsia, L.-C., Lim, G.H., Pandey, S.M., See, G.H., Shangguan, W., Zhou, X., Zhu, Z.,

*NTU, SG*Short-channel effects (SCEs) for both intrinsic chargesand extrinsic capacitances need to be modeled when theMOSFET channel is short. The intrinsic SCEs are modeled using bulk-charge sharing and quasi-two dimensional potential barrier loweirng; extrinsic overlap capacitances [...]

### Compact Modeling of Nonlinearities in Submicron MOSFETs

da Silva, P.D., de Sousa, F.R., Montoro, C.G., Schneider, M.C.,

*Federal University of Santa Catarina, BR*Low power operation in RF CMOS circuits requiring low-distortion levels is often difficult to achieve due to the exponential relationship between drain current (IDS) and gate-to-source voltage (VGS) in subthreshold region. Our contribution in this work [...]

### On the Compact Modelling of Induced Gate Noise in the MOS Transistor

This work presents a analytical model to calculate gate related noise parameters for any arbitrary velocity field relationship and discusses some finer point of diffusivity modeling and impact of those effect on gate related noise [...]

### Comprehensive Characterization and Analysis of RTS, 1/f, RF Noise and Power Performances of Schottky-Diode in Standard CMOS

Kwong, D.L., Lo, G.Q., Loh, W.Y., Shi, J.L., Xiong, Y.Z., Yu, M.B.,

*Institute of Microelectronics, Singapore, SG*This study presents comprehensive characterization of Schottky-diode in standard CMOS on its DC, low-frequency and RF noise performance. Random-telegraph-signal (RTS) and 1/f noise have been characterized, along with RF noise, power performances analysis. Results showed [...]

### Two-Tone Distortion Modeling for SiGe HBTs Using the High-Current Model

Borich, V., Chen, S., Malladi, R.R., Newton, K.M., Rascoe, J., Sweeney, S.L., Venkatadri, S., Yang, J.,

*IBM Systems and Technology, US*This paper examines certain aspects of the base resistance model of HiCUM (High Current Model) to address convergence problems seen during 2-tone distortion simulations of SiGe HBTs. Here, we propose some changes to the model [...]

### BSIM Model for MOSFET Flicker Noise Statistics: Technology Scaling, Area, and Bias Dependence

We have implemented a statistical model for MOSFET flicker noise as an extension to BSIM. Model development methodology and hardware correlation for various types of MOSFETs from 180nm and 130nm technology nodes are presented. Given [...]

### Investigation of Substrate Current Effects and Modeling of Substrate Resistance Network for RFCMOS

RF device models focus on device performance in the high frequency region, with a reasonable DC model. The substrate current (Isub) is often regarded as unimportant in the DC model and thus ignored because the [...]

### TCAD-based Process Dependant HSPICE Model Parameter Extraction

This paper describes the methodology for global extraction of HSPICE compact model parameters as explicit polynomial functions of process parameter variations (halo dosage, gate oxidation temperature etc). Electrical data required for extraction is obtained from [...]

### Analysis and Modeling of NQS Effects in MOSFET’s

Three issues regarding NQS effect in MOSFET’s are investigated: When NQS effect becomes significant, NQS effect on channel charge partition, and its implementation in advanced MOSFET models (PSP, Hisim2 and Bsim4).Channel segmentation method [1] with [...]

### Compact Capacitance Model of LDMOS for Circuit Simulation

Capacitance modeling in LDMOS is much more complicated than that in bulk MOSFET’s due to the fact of non-uniform lateral channel doping, the extended gate drain overlap region and its interaction with channel charges. Measurements [...]

### Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach

Chandrasekaran, K., Chiah, S.B., Rustagi, S.C., See, G.H., Shangguan, W., Singh, N., Zhou, X., Zhu, Z.M.,

*Nanyang Technological University, SG*A compact model for the explicit surface potential equation of doped symmetric double-gate MOSFET from Poisson equation with regional approach is presented. It’s scalable for all doping and channel thicknesses and has been proved to [...]

### Explicit Threshold Voltage Based Compact Model of Independent Double Gate MOSFET

This paper describes an explicit compact model of Independent Double Gate (IDG) MOSFET with undoped channel. The validity of this model is demonstrated by comparisons with Atlas simulations. The model was implemented in VerilogA in [...]

### Capacitance Model for Four-Terminal DG MOSFETs

Hioki, M., Koike, H., Nakagawa, T., O’uchi, S., Sekigawa, T., Tsutsumi, T.,

*National Institute of Advanced Industrial Science and Technology, JP*We present an intrinsic-capacitance model for undoped-channel full-deplete DG MOSFETs with two independent gates of different gate-oxide thickness. It includes carrier-velocity saturation, and mobility change by the surface electric-field. We considered five intrinsic capacitances Cg1s, [...]

### A Computationally Efficient Method for Analytical Calculation of Potentials in Undoped Symmetric DG SOI MOSFET

In order to build an analytical model of an undoped symmetric DG SOI MOSFET devices, an accurate but rather difficult method was used by S. Malobabic et.al. [2] in their papers that is based on [...]

### Compact Model of drain-current in Double-Gate MOSFETs including carrier quantization and short-channel effects

Double-Gate (DG) structure has been in the last years the object of intensive research because its enormous potentiality to push back the integration limits to which conventional devices are subjected. Although the operation of DG [...]

### Compact modeling and performance analysis of Double-Gate MOSFET-based circuits

Double-Gate (DG) MOS transistors and related multiple-gate device architectures are nowadays widely identified as one of the most promising solutions for meeting the roadmap requirements for the end-of-the-roadmap integration. One of the identified challenges for [...]

### Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability

We have modeled a new structure TRIMGAS which has 3 gate materials in the gate and an oxide stack. we have compared various parameters to see whether this strucure is superior to any of our [...]

### Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs

In the present paper, a compact model for short channel effects (SCEs) in source/drain engineered nanoscale DG MOSFET, is proposed for the first time and the impact of spacer width (s), lateral source/drain doping gradient [...]

### Compact Models for Double Gate and Surrounding Gate MOSFETs

The models presented by Lu and Taur, [1], for lightly doped double gate and surrounding gate MOSFETs each require numerical solution of a transcendental equation. In this paper we present explicit, analytic solutions of these [...]

### SOI CMOS Compact Modeling based on TCAD Device Simulations

This work describes a TCAD-based methodology for generating compact models for circuit design in advance of hardware availability (predictive modeling). The exercise was performed on a 65nm node SOI CMOS technology. TCAD simulations accurate enough [...]

### On Idlow with Emphasis on Speculative SPICE Modeling

An, J.X., Assad, F., Chen, Q., Goo, J-S, Icel, A.B., Krishnan, S., Ly, T., Radwin, M., Subba, N., Suryagandh, S., Thuruthiyil, C., Wu, Z-Y, Yonemura, J.,

*Advanced Micro Devices, US*An empirical correlation model of Idlow, the MOSFET drain current measured at Vgs=Vdd/2 and Vds=Vdd, where Vdd is the supply voltage, is proposed based on the alpha-power law model. It enables a comprehensive analysis of [...]

### Dynamic Behavior Model for High-k MOSFETs

High-K dielectrics need to be introduced into bulk CMOS to extend the scaling limits. However, the use of high-k dielectrics introduces new dynamic behavior into transistor operation. Pulsed measurements show hysteresis in drain current (Id), [...]

### A Simple Yet Accurate Mismatch Model For Circuit Simulation

As technology scales, mismatch between a pair of transistors becomes a more and more critical issue for technology development and circuit designs. Scaling also increases the complexity of compact device modeling. Sophisticated models are usually [...]

### Enhanced Junction Capacitance Modeling

The current standard diode junction capacitance models do not yield high quality models for hyperabrupt junction varactors that are constructed from several implants. We describe a new enhancement that employs the actual (exponential) doping profiles [...]

### A Compact Model of Ballistic CNFET for Circuit Simulation

As silicon technology is approaching to its limit, Carbon nanotube FETs (CNFET) are shown to have potential of taking this place in the post silicon era. Consequently, interests have grown to predict the performance of [...]

### A Circuit-Compatible Model for Ballistic Silicon Nanowire Transistors

Silicon nanowire transistors (SNWT) are being extensively explored as a successor to CMOS. Silicon nanowires with a diameter as small as 2nm and having high carrier mobility have been achieved. Such developments shed light on [...]

### Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs

A simplae compact model for the threshold voltage of Strained Si/SiGe MOSFET is reported for the first time. This model accurately predicts the effects of Ge content and other device parameters on threshold voltage. The [...]

### Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology

Chidambarrao, D., McCullen, J.H., Mitchell, T.G., Narasimha, S., Onsongo, D., Williams, R.Q.,

*IBM Corporation, US*This work presents a novel methodology for a physically-based, layout-dependent nitride liner stress model that works with readily-available compact models. The methodology includes a data-calibrated, semi-empricial model and is tightly-coupled to circuit netlist extraction for [...]

### A transient circuit model for a phase change memory element

A transient lumped element model for a phase change memory (PCM) cell is developed for use in a circuit simulator. Unlike existing models, this model calculates threshold voltage and off-state resistance drift as found in [...]

### Static Analog Design Methodology

When strong constraints of supply voltage (< 1V ) and bias current (< 100nA) are required, the only way to meet design’sspecifications without using huge silicon area consists on decreasing transistor’s inversion level and therefore [...]

### Interrelations between Threshold Voltage Definitions and Extraction Methods

Cunha, A.I.A., Galup-Montoro, C., Machado, M.B., Schneider, M.C.,

*Federal University of Santa Catarina, BR*This paper presents a brief discussion on the main MOSFET threshold voltage definitions available in the literature as well as on associated extraction methodologies. In order to compare these definitions and methodologies, we take advantage [...]

### A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram

A unified parameters extraction procedure for temperature and geometry scalable bipolar transistor model Mextram has been demonstrated using an example of high-speed SiGe HBT technology. The essential feature of the proposed methodology is a direct [...]

### Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors

In this communication we present a charge-based formulation for the thermal noise in short-channel MOS transistors. We arrive at a closed expression for the channel noise including velocity saturation for all the operating regions of [...]

Journal: TechConnect Briefs

Volume: 3, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3

Published: May 7, 2006

Industry sector: Sensors, MEMS, Electronics

Topics: Compact Modeling

ISBN: 0-9767985-8-1