High-K dielectrics need to be introduced into bulk CMOS to extend the scaling limits. However, the use of high-k dielectrics introduces new dynamic behavior into transistor operation. Pulsed measurements show hysteresis in drain current (Id), threshold-voltage (Vth) instability and Id degradation. In order to design and verify circuits with high-k MOSFETs, it is thus necessary for the device models to capture the dynamic behavior.
In this work, an analytical model is derived to capture the dynamic behavior of a high-k transistor by modeling the fast transient charging effects. Traps associated with the high-k layer get charged/discharged changing the threshold voltage of transistor dynamically. WKB theory is used to derive the rate of change of occupancy of these traps by considering various possible trapping mechanisms such as direct trap tunneling, gate current, etc. The final model is verified against experimental data from literature. In order for the model to be efficiently implemented in a compact model framework, a sub-circuit architecture is designed. The sub-circuit is placed in parallel with the intrinsic transistor in any compact model and solved simultaneously to dynamically change the threshold voltage and thus capture the dynamic behavior of the transistor.
Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 7, 2006
Pages: 835 - 838
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling