Nakagawa T. – TechConnect Briefs

HiSIM-SOTB: A Compact Model for SOI-MOSFET with Ultra-Thin Si-Layer and BOX

Miura-Mattausch M., Kikuchihara H., Feldmann U., Nakagawa T., Miyake M., Iizuka T., Mattausch H.J., Miura-Mattausch M., Hiroshima University, JP

The Silicon-On-Thin-Buried-Oxide (SOTB) transistor is a descendant of the conventional SOI MOSFET with thin Silicon and BOX layers. Many different structure and material variations are possible, where the choice of a thicker BOX may be [...]

Source/Drain Edge Modeling for DG MOSFET Compact Model

Nakagawa T., O’uchi S., Sekigawa T., Tsutsumi T., Hioki M., Koike H., AIST (National Institute of Advanced Industrial Science and Technology), JP

A compact model for four terminal double-gate MOSFET, based on double charge-sheet approximation with carrier velocity saturation, is discussed. Although it is a monolithic model both for conductance and intrinsic capacitances, it is not a [...]

Comparison of Four-terminal DG MOSFET Compact Model with Thin Si channel FinFET Devices

Nakagawa T., Sekigawa T., Tsutsumi T., Liu Y., Hioki M., O’uchi S., Koike H., Electroinformatics Group, JP

We have proposed a compact model for four-terminal double-gate MOSFETs based on double charge-sheet model. The model can handle asymmetric gate structure such as different gate-oxide thickness, as well as independent gate voltage for two [...]

Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation

Miura-Mattausch M., Chan M., He J., Koike H., Mattausch H.J., Miura-Mattausch M., Nakagawa T., Park Y.J., Tsutsumi T., Yu Z., Hiroshima University, JP

We are reporting the construction of a common platform for compact model development based on the Verilog-A language and in particular a framework for efficient development of multi-gate MOSFET models for circuit simulation. Phenomena expected [...]

Transition Point Consideration for Velocity Saturating Four-terminal DG MOSFET Compact Model

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., O’uchi S., Koike H., AIST, JP

We have proposed a compact model for four-terminal DG MOSFETs based on double charge-sheet model, with the velocity saturation effect as a function of carrier density profile inside the channel, with explicit handling of drain [...]

Capacitance Model for Four-Terminal DG MOSFETs

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., O’uchi S., Koike H., National Institute of Advanced Industrial Science and Technology, JP

We present an intrinsic-capacitance model for undoped-channel full-deplete DG MOSFETs with two independent gates of different gate-oxide thickness. It includes carrier-velocity saturation, and mobility change by the surface electric-field. We considered five intrinsic capacitances Cg1s, [...]

Device Parameter Extraction from Fabricated Double-Gate MOSFETs

Tsutsumi T., Liu Y., Nakagawa T., Sekigawa T., Hioki M., Suzuki E., Koike H., National Institute of Advanced Industrial Science and Technology (AIST), JP

Accurate spice simulation needs parameter extraction of the fabricated DG-MOSFETs with good electrical characteristics. However, it is very difficult to fabricate such good DG-MOSFETs, so that device parameter extraction of the fabricated DG-MOSFETs has been [...]

Compact Model for Ultra-Short Channel Four-Terminal DG MOSFETs for Exploring Circuit Characteristics

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., Suzuki E., Koike H., National Institute of Advanced Industrial Science and Technology (AIST), JP

We have proposed a compact model of the DG MOSFETs which handles two gates independently. The model can simulate the DG MOSFETs of asymmetric gate design, together with their four-terminal operation. In this report, we [...]

Improved Compact Model for Four-Terminal DG MOSFETs

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., Suzuki E., Koike H., National Institute of Advanced Industrial Science and Technology, JP

Double-gate field-effect transistors are promising device structures which have excellent scalability. To evaluate merits of DG MODFETs, we developed a compact four-terminal DG MOSFET model by adopting the double charge-sheet model. In this presentation, we [...]

Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode

Nakagawa T., Sekigawa T., Tsutsumi T., Suzuki E., Koike H., Electroinformatics Group, AIST, JP

Recently, a double-gate structure has attracted much attention as an emerging device concept. The DG MOSFET is regarded as the most scalable device. Usually the DG MOSFET is supposed to be used as a three-terminal [...]