Three general classes of solutions are needed to model an arbitrary double-gate (DG) metal-oxide-semiconductor (MOS) capacitor with arbitrary bias conditions. The “zero-field” (F0) and the “zero-potential” (P0) solution regimes are separated by the “zero-field and zero-potential” (PF0) solution. Based on the F0 solution, an approximate expression is proposed to explicitly relate the potential (ψc) and the electric field (Ec) on the silicon side of the oxide/silicon interface of a symmetrical DG MOS capacitor. It is the basis on which the threshold voltage and the current-voltage (IV) models of a symmetrical DG MOS field-effect transistor are developed. An improved IV model is presently developed using the proposed ψc-Ec relationship and incorporating also the mobility degradation effect at high vertical electric field and the velocity saturation effect at high lateral electric field. Comparisons are made among the presently proposed IV model, the previously proposed IV model and numerical simulations.
Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 7, 2006
Pages: 692 - 697
Industry sector: Sensors, MEMS, Electronics
Topics: Compact Modeling