High-Voltage LDMOS Compact Modeling

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In compact modeling of high-voltage LDMOS devices often a sub-circuit approach is used. While for the channel region a standard compact MOS model (for example BSIM4, MM11 or PSP) is used, the drift region is described by a compact JFET model. We will show that using this conventional approach
the effects of the widening of the depletion region in the lateral direction can not be taken into account properly.
As a consequence the voltage at the internal node between channel and drift region becomes unphysical and accurate
physics-based capacitance modeling becomes unfeasible.
In this paper we will introduce a new approach for compact LDMOS modeling to remedy these shortcomings. Next we describe the method to implement this approach in a circuit simulator. Finally a comparison of measurements and simulations is presented for both currents and capacitances.

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Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 7, 2006
Pages: 714 - 719
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 0-9767985-8-1