SOI CMOS Compact Modeling based on TCAD Device Simulations

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This work describes a TCAD-based methodology for generating compact models for circuit design in advance of hardware availability (predictive modeling). The exercise was performed on a 65nm node SOI CMOS technology. TCAD simulations accurate enough for predicting quantitative results require a novel calibration methodology to hardware over broad geometry, bias, and temperature ranges. NFET and PFET compact models were extracted from TCAD-generated
I-V data and the quality of model fit was shown to be very good.

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Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 7, 2006
Pages: 828 - 830
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 0-9767985-8-1