Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs


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In the present paper, a compact model for short channel effects (SCEs) in source/drain engineered nanoscale DG MOSFET, is proposed for the first time and the impact of spacer width (s), lateral source/drain doping gradient (d) and their ratio i.e. c (= s/d) on – Threshold voltage (Vth) and Subthreshold slope (S) is analyzed extensively. Source/Drain extension region engineering is modeled through the effective channel length (Leff), which is defined as a function of peak source/drain doping level (NSD), gate length (Lg), s and d. The dependence of Leff on s, d and c is analyzed in detail. We show that the condition c > 7Tsi/Lg must be maintained in order to minimize SCEs in source/drain engineered devices as compared to abrupt source/drain devices. A reasonable agreement of the modeled Vth and S with simulated data is obtained for the entire range of s ((0.25)Lg – (1.0)Lg), d (1 – 6 nm/dec) and Leff (60 nm – 20 nm) for film thickness (Tsi) of = (0.4)Lg and (0.6)Lg at the drain bias (Vds) of 50mV and 1.1V, showing the validity of the proposed model for the accurate estimation of SCEs in source/drain engineered nanoscale DG MOSFETs.

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Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 7, 2006
Pages: 820 - 823
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 0-9767985-8-1