Based on our framework model of the electrostatics and the drain current in short-channel, nanoscale DG and GAA MOSFETs, we here present a corresponding model for the device capacitances covering all regimes of operation from [...]
As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as promising candidates for future generation device building blocks. This trend poses new challenges in developing [...]
The quantum mechanical effect (QME) in nanoscale MOSFETs has become more and more important. The quantization of the space charge density in bulk-MOS compact models is usually modeled by the van Dort model with a [...]
The quasi-2D method has been used to account for short-channel effects in PN-junction MOSFETs. Recently some authors applied the quasi-2D solution to SB MOSFETs to derive potential profiles. In this paper, an improved quasi-2D solution [...]
, He J.
, Koike H.
, Mattausch H.J.
, Miura-Mattausch M.
, Nakagawa T.
, Park Y.J.
, Tsutsumi T.
, Yu Z.
, Hiroshima University, JP
We are reporting the construction of a common platform for compact model development based on the Verilog-A language and in particular a framework for efficient development of multi-gate MOSFET models for circuit simulation. Phenomena expected [...]
Double-gate MOSFET is one of the key potential devices to allow further extension of CMOS technology scaling. The compact modeling community faces great challenges to model the physical effects due to the coupling of the [...]
Surface potential is one key variable in DG MOSFET compact modeling. A complete surface potential versus voltage equation and its continuous solution from the accumulation to strong inversion region are presented in this paper for [...]
Advanced MOSFETs exploit the carrier confinement to suppress the short-channel effect, which is realized by reducing the bulk layer thickness. The ongoing developments of the multi-gate MOSFET as well as the fully-depleted SOI-MOSFET with ultra [...]
Electromigration (EM) is the transport of atoms and ions in metals at high electrical current density (>100kA/cm^2) leaving behind voids. It was delineated in 1961 by Huntington  in gold wire, and empirically modeled by [...]
Last a few years have witnessed a quick rise of Verilog-A language as a new standard for compact model development. Consequently there are significant interests in developing softwares which compiles compact models defined in Verilog-A [...]
A new enhancement on modeling ‘snapback’ in MOS transistors for ESD simulation is presented. The model uses standard industry models only and intrinsically includes all major physical effects in snapback. An ESD snapback MOS model [...]
Existing equations for describing the layout dependent base resistance are improved and extended for heterojunction bipolar transistors (HBTs) in advanced process technologies. The new equations have been developed using quasi-3D device simulation and have been [...]
Field effect transistor (FET) was conceived 80 years ago in Lilienfeld ‘s 1926 1932 patents . Shockley 1952  invented the volume channel FET 55 years ago using two opposing p/n junctions as gates on [...]
Latest advances are presented on theoretical device and circuit characterizations of the Bipolar Field effect transistor (BiFET) . The 2 Dimensional (2 D) rectangular geometry of the transistor (uniform in the width direction) is employed [...]
Compact MOSFET noise models are mostly based on the Klaassen-Prins (KP) method. However, the noise properties of lateral nonuniform MOSFETs are considerably different from the prediction obtained with the conventional KP based methods which, at [...]
Since past three decades, in the pursuit of superior performances relative to high-speed circuits and packing density, miniaturization of device dimensions has been adopted as a powerful tool. Gradually, as device feature sizes move into [...]
We present an innovative method to model the spatial correlations in semiconductor process and device variations or in VLSI circuit variations. Without using the commonly adopted PCA approach, we give a very compact expression to [...]
, Chiney P.
, Icel A.
, Krishnan S.
, Rathor M.
, Subba N.
, Suryagandh S.
, Wason V.
, Wu Z-Y
, Advanced Micro Devices, US
Analog design uses transistors with longer channel length for high performance. gm, Rout and intrinsic gain form the matrix to gauge this performance. It is critical to design these circuits for manufacturing variability. This work [...]
The impressive downscaling of CMOS technology and its more and more massive introduction in System-on-chip (SoC) oriented applications require comprehensive modeling approach able to describe such different world (digital and analog) starting from a single [...]
We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (Ipeak) is a key parameter. Ieff is commonly defined as the average [...]
As the MOSFET continues to shrink rapidly, emerging physical phenomena, such as ballistic transport, have to be considered in the modelling and simulation of ultra-scaled devices. Future Double-Gate MOSFETs, designed with channel lengths in the [...]
, Lee F.
, Li F.
, Liu W.
, Subba N.
, Tudor B.
, Wang P.
, Wang W.
, Xi X.
, Synopsys, Inc., US
The impact ionization (II) model accuracy issue in industry standard SOI MOSFET is discussed in the paper. Based on Medici 2D simulation study, an improved impact ionization model is proposed which can capture the voltage [...]
In the sub 100-nm regime, MOSFET parameter extraction has become a challenging task. Commonly used gradient based methods have many difficulties such as good initial guess requirement, singularities in objective functions, etc. Genetic Algorithm (GA), [...]
This paper is a continuation of the work we presented in the 2006 IEEE UGIM Proceedings. Iterative compact device models with quantum mechanical effects for a Double Gate (DG) MOSFET are presented using the Lambert [...]
FinFETs are very promising for low power, low voltage portable applications. For nano-circuit simulation, a suitable FinFET model is required. A behavioural model based on a neural network has been developed in this work and [...]
In this paper we present a completely closed-form inversion charge-based model for the drain current and conductance of a symmetric double-gate MOSFET based on the drift-diffusion transport mechanism, that takes into account vertical field mobility [...]
We have proposed a compact model for four-terminal double-gate MOSFETs based on double charge-sheet model. The model can handle asymmetric gate structure such as different gate-oxide thickness, as well as independent gate voltage for two [...]
Advanced compact models are evaluated for simulation of mixed analog-digital circuits working at low temperature (77 to 200 K). This evaluation is performed on a dual gate oxide CMOS technology with 0.18 µm / 1.8 [...]
The interface traps and trapped charges along the surface channel region are generated during transistor stress or operation and primarily responsible for the changes of device properties. The threshold voltage is varied by the generation [...]
In this paper, compact analytical threshold voltage model for multi-layered-gate electrode workfunction engineered recessed channel (MLGEWE-RC) MOSFET is presented and investigated using ATLAS device simulator. The novel device continues merits of recessed channel and dual [...]
Double-Gate structures with independent gates have been recently proposed, allowing a four terminal operation. Independent Double-Gate (IDG) MOSFETs offer additional potentialities, such as a dynamic threshold voltage control by one of the two gates, transconductance [...]
We have already developed an explicit threshold voltage based compact model of independent double gate MOSFET which well works for gate length between 30 nm and 1µm, or more. However, the mobility was assumed constant. [...]
In this paper, a technique for constructing the RTS noise model based on the statistical analysis of the noise data obtained from the Schottky diode under different biases is introduced. The three RTS parameters: pulse [...]
In the present work, a new structural concept, non-uniformly doped multilayered asymmetric gate stack (ND-MAG) surrounding gate MOSFET has been proposed and it has been demonstrated using analytical modeling and simulation that ND-MAG SGT leads [...]
, Kajiwara T.
, Mattausch H.J.
, Miura-Mattausch M.
, Miyake M.
, Oritsuki Y.
, Sadachika N.
, Sakuda T.
, Yokomiti M.
, Hiroshima University, JP
We present here the high-voltage MOSFET model HiSIM-HV based on the complete surface-potential description. The model is valid both for symmetrical and asymmetrical structures with scaling properties for any structural variations valid for wide range [...]
, Dasarapu V.K.
, Krishnamurthy S.
, Lin X-W
, Mahotin Y.
, Mukherjee P.
, Roger F.
, Ryles R.
, Uppal S.
, Synopsys, Inc., US
This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parametersfrom silicon data. The robustness of this methodology was tested [...]
Journal: TechConnect Briefs
Volume: 3, Nanotechnology 2008: Microsystems, Photonics, Sensors, Fluidics, Modeling, and Simulation – Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: June 1, 2008
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling