Park J-E – TechConnect Briefs

Effective Drive Current in CMOS Inverters for Sub-45nm Technologies

Freeman G., Hu J., Park J-E, Wong H.S.P., Stanford University, US

We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (Ipeak) is a key parameter. Ieff is commonly defined as the average [...]

Simulating CMOS Circuits Containing Multiple FET Types Including the Geometric Dependence of Correlation between FET Types

Assenmacher J., Liang C-H, Park J-E, Park S-J, Wachnik R., Watts J., IBM, US

MOSFET device of similar design but different threshold voltage are often built on a single chip. It is important to be able to simulate with a compact model the variation of such devices including the [...]

Modeling MOSFET Process Variation using PSP

Lee Y.M., Park J-E, Watts J.S., IBM, US

The PSP model has been extensively evaluated for it’s abililty accurately match IV and CV characteristics MOSFETs measured on a single die. This enables accurate prediction of circuit behavior for circuits made of transistors which [...]