Effective Drive Current in CMOS Inverters for Sub-45nm Technologies

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We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (Ipeak) is a key parameter. Ieff is commonly defined as the average between IH and IL, where IH=Ids(Vgs=Vdd, Vds=0.5Vdd) and IL = Ids(Vgs=0.5Vdd, Vds=Vdd). In the past, this Ieff definition has been accurate in modeling the inverter delay. However, we find that as devices are scaled further into the nanoscale regime, the maximum transient current can deviate severely from IH, in which case, another metric should be used. The deviation of Ipeak from IH is found to increase as delay decreases or as device overdrive voltage increases. We define Ieff = (Ipeak+IM+IL)/ 3, where IM = Ids(Vgs=0.75Vdd, Vds=0.75Vdd). We evaluate our model against others by comparing the analytical and HSPICE extracted Ieff ratios across devices of varying threshold voltages, VTH. Our model is shown to better capture changes in VTH/Vdd, which are important since Vdd has not been scaled much, while VTH still remains a design parameter for the sub-45nm technologies.

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Journal: TechConnect Briefs
Volume: 3, Nanotechnology 2008: Microsystems, Photonics, Sensors, Fluidics, Modeling, and Simulation – Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: June 1, 2008
Pages: 829 - 832
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 978-1-4200-8505-1