Interface-trap Charges on Recombination DC Current-Voltage Characteristics in MOS transistors

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The interface traps and trapped charges along the surface channel region are generated during transistor stress or operation and primarily responsible for the changes of device properties. The threshold voltage is varied by the generation of interface-trap charges and eventually causes the transistor to cease functioning within the design parameters. In the paper, steady-state Shockley-Read-Hall kinetics is employed to explore the interface-trap charges at the SiO2/Si interface on the electron-hole recombination direct-current current-voltage (R-DCIV) properties in MOS field-effect transistors. Extensive analysis includes device parameter variations of interface-trap density NIT, dopant impurity concentration PIM, oxide thickness XOX, forward source/drain junction bias VPN, and transistor temperature T in order to provide a comprehensive baseline that can be used to guide the analysis of experimental measurements.

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Journal: TechConnect Briefs
Volume: 3, Nanotechnology 2008: Microsystems, Photonics, Sensors, Fluidics, Modeling, and Simulation – Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: June 1, 2008
Pages: 869 - 872
Industry sector: Sensors, MEMS, Electronics
Topics: Compact Modeling
ISBN: 978-1-4200-8505-1