Modeling of Spatial Correlations in Process, Device, and Circuit Variations


Keywords: , , , ,

We present an innovative method to model the spatial correlations in semiconductor process and device variations or in VLSI circuit variations. Without using the commonly adopted PCA approach, we give a very compact expression to represent a given spatial correlations among a set of similar statistical variables/instances located at different places on a chip/die. Our compact expression is easy for implementation in a SPICE model and is efficient in circuit simulations. In semiconductor processes and devices as well as in logic circuits, the degree of correlation between any two intra-die instances of a process/device/ circuit decreases with increasing separation between them. Various measured hardware data has revealed such a gradual de-correlation of spatial correlation over distance. Describing intra-die variations using spatial (i.e., distance-dependent) correlations unifies various descriptions of intra-die variations, such as mismatch, across chip variations, random uncorrelated variations, and random correlated variations, etc.

PDF of paper:

Journal: TechConnect Briefs
Volume: 3, Nanotechnology 2008: Microsystems, Photonics, Sensors, Fluidics, Modeling, and Simulation – Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: June 1, 2008
Pages: 818 - 821
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 978-1-4200-8505-1