Papers:
Capacitance modeling of Short-Channel DG and GAA MOSFETs
Based on our framework model of the electrostatics and the drain current in short-channel, nanoscale DG and GAA MOSFETs, we here present a corresponding model for the device capacitances covering all regimes of operation from [...]
New Properties and New Challenges in MOS Compact Modeling
Zhou X., See G.H., Zhu G., Zhu Z., Zhu G., Zhu Z., Lin S., Wei C., Srinivas A., Zhang J., Nanyang Technological University, SG
As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as promising candidates for future generation device building blocks. This trend poses new challenges in developing [...]
Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Quantum-Mechanical Effects
See G.H., Zhou X., Zhu G., Zhu Z., Zhu G., Zhu Z., Lin S., Wei C., Zhang J., Srinivas A., Nanyang Technological University, SG
The quantum mechanical effect (QME) in nanoscale MOSFETs has become more and more important. The quantization of the space charge density in bulk-MOS compact models is usually modeled by the van Dort model with a [...]
Quasi-2D Surface-Potential Solution to Three-Terminal Undoped Symmetric Double-Gate Schottky-Barrier MOSFETs
Zhu G., Zhu Z., See G.H., Zhou X., Zhu G., Zhu Z., Lin S., Wei C., Zhang J., Srinivas A., Nanyang Technological University, SG
The quasi-2D method has been used to account for short-channel effects in PN-junction MOSFETs. Recently some authors applied the quasi-2D solution to SB MOSFETs to derive potential profiles. In this paper, an improved quasi-2D solution [...]
Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation
Miura-Mattausch M., Chan M., He J., Koike H., Mattausch H.J., Miura-Mattausch M., Nakagawa T., Park Y.J., Tsutsumi T., Yu Z., Hiroshima University, JP
We are reporting the construction of a common platform for compact model development based on the Verilog-A language and in particular a framework for efficient development of multi-gate MOSFET models for circuit simulation. Phenomena expected [...]
Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Any Body Doping
See G.H., Zhou X., Zhu G., Zhu Z., Zhu G., Zhu Z., Lin S., Wei C., Zhang J., Srinivas A., Nanyang Technological University, SG
Double-gate MOSFET is one of the key potential devices to allow further extension of CMOS technology scaling. The compact modeling community faces great challenges to model the physical effects due to the coupling of the [...]
Modeling of Floating-Body Devices Based on Complete Potential Description
Sadachika N., Murakami T., Ando M., Ishimura K., Ohyama K., Miyake M., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Hiroshima University, JP
Advanced MOSFETs exploit the carrier confinement to suppress the short-channel effect, which is realized by reducing the bulk layer thickness. The ongoing developments of the multi-gate MOSFET as well as the fully-depleted SOI-MOSFET with ultra [...]
The Driftless Electromigration Theory (Diffusion-Generation-Recombination-Trapping)
Electromigration (EM) is the transport of atoms and ions in metals at high electrical current density (>100kA/cm^2) leaving behind voids. It was delineated in 1961 by Huntington [1] in gold wire, and empirically modeled by [...]
Adaptable Simulator-independent HiSIM2.4 Extractor
This paper presents a method and its software implementation to extract Spice parameters of the HiSIM2.4 model. The completed flow of dedicated parameter extraction procedures is currently designed for the HiSIM2.4 model and can be [...]
Recent Advancements on ADMS Development
Last a few years have witnessed a quick rise of Verilog-A language as a new standard for compact model development. Consequently there are significant interests in developing softwares which compiles compact models defined in Verilog-A [...]
Source/Drain Junction Partition in MOS Snapback Modeling for ESD Simulation
A new enhancement on modeling ‘snapback’ in MOS transistors for ESD simulation is presented. The model uses standard industry models only and intrinsically includes all major physical effects in snapback. An ESD snapback MOS model [...]
Improved layout dependent modeling of the base resistance in advanced HBTs
Existing equations for describing the layout dependent base resistance are improved and extended for heterojunction bipolar transistors (HBTs) in advanced process technologies. The new equations have been developed using quasi-3D device simulation and have been [...]
The Bipolar Field-Effect Transistor Theory (A. Summary of Recent Progresses)
Field effect transistor (FET) was conceived 80 years ago in Lilienfeld ‘s 1926 1932 patents [1]. Shockley 1952 [2] invented the volume channel FET 55 years ago using two opposing p/n junctions as gates on [...]
The Bipolar Field-Effect Transistor Theory (B. Latest Advances)
Latest advances are presented on theoretical device and circuit characterizations of the Bipolar Field effect transistor (BiFET) [1]. The 2 Dimensional (2 D) rectangular geometry of the transistor (uniform in the width direction) is employed [...]
An Accurate and Versatile ED- and LD-MOS Model for High-Voltage CMOS IC Spice Simulation
The paper presents a high-voltage compact MOSFET model that has been proven physically accurate and numerically robust for various and generations of high-voltage ED (extended drain) and LD (laterally double diffused) production CMOS process technologies. [...]
Compact Modeling of Noise in non-uniform channel MOSFET
Compact MOSFET noise models are mostly based on the Klaassen-Prins (KP) method. However, the noise properties of lateral nonuniform MOSFETs are considerably different from the prediction obtained with the conventional KP based methods which, at [...]
An Iterative Approach to Characterize Various Advanced Non-Uniformly Doped Channel Profiles
Since past three decades, in the pursuit of superior performances relative to high-speed circuits and packing density, miniaturization of device dimensions has been adopted as a powerful tool. Gradually, as device feature sizes move into [...]
Model Implementation for Accurate Variation Estimation of Analog Parameters in Advanced SOI Technologies
Suryagandh S., Subba N., Wason V., Chiney P., Wu Z-Y, Chen B.Q., Krishnan S., Rathor M., Icel A., Advanced Micro Devices, US
Analog design uses transistors with longer channel length for high performance. gm, Rout and intrinsic gain form the matrix to gauge this performance. It is critical to design these circuits for manufacturing variability. This work [...]
Modeling of gain in advanced CMOS technologies
The impressive downscaling of CMOS technology and its more and more massive introduction in System-on-chip (SoC) oriented applications require comprehensive modeling approach able to describe such different world (digital and analog) starting from a single [...]
Effective Drive Current in CMOS Inverters for Sub-45nm Technologies
We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (Ipeak) is a key parameter. Ieff is commonly defined as the average [...]
Process Aware Compact Model Parameter Extraction for 45 nm Process
Karmarkar A.P., Dasarapu V.K., Saha A.R., Braun G., Krishnamurthy S., Lin X-W, Synopsys (India) Pvt. Ltd., IN
The current industry trends call for smaller devices and decreasing feature sizes with each technology node. The process variability has a significant impact on the device characteristics for deep sub-micron technologies because of the smaller [...]
Analytical Modelling and Performance Analysis of Double-Gate MOSFET-based Circuit Including Ballistic/quasi-ballistic Effects
As the MOSFET continues to shrink rapidly, emerging physical phenomena, such as ballistic transport, have to be considered in the modelling and simulation of ultra-scaled devices. Future Double-Gate MOSFETs, designed with channel lengths in the [...]
An Improved Impact Ionization Model for SOI Circuit Simulation
Xi X., Li F., Liu W., Tudor B., Wang P., Wang W., Liu W., Lee F., Wang P., Wang W., Subba N., Goo J-S, Synopsys, Inc., US
The impact ionization (II) model accuracy issue in industry standard SOI MOSFET is discussed in the paper. Based on Medici 2D simulation study, an improved impact ionization model is proposed which can capture the voltage [...]
Parameter Extraction for Advanced MOSFET Model using Particle Swarm Optimization
In the sub 100-nm regime, MOSFET parameter extraction has become a challenging task. Commonly used gradient based methods have many difficulties such as good initial guess requirement, singularities in objective functions, etc. Genetic Algorithm (GA), [...]
Compact Models for Double Gate MOSFET with Quantum Mechanical Effects using Lambert Function
This paper is a continuation of the work we presented in the 2006 IEEE UGIM Proceedings. Iterative compact device models with quantum mechanical effects for a Double Gate (DG) MOSFET are presented using the Lambert [...]
Neural Computational Approach for FinFET Modeling and Nano-Circuit Simulation
FinFETs are very promising for low power, low voltage portable applications. For nano-circuit simulation, a suitable FinFET model is required. A behavioural model based on a neural network has been developed in this work and [...]
Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field-dependent Mobility and Body Doping
In this paper we present a completely closed-form inversion charge-based model for the drain current and conductance of a symmetric double-gate MOSFET based on the drift-diffusion transport mechanism, that takes into account vertical field mobility [...]
Comparison of Four-terminal DG MOSFET Compact Model with Thin Si channel FinFET Devices
Nakagawa T., Sekigawa T., Tsutsumi T., Liu Y., Hioki M., O’uchi S., Koike H., Electroinformatics Group, JP
We have proposed a compact model for four-terminal double-gate MOSFETs based on double charge-sheet model. The model can handle asymmetric gate structure such as different gate-oxide thickness, as well as independent gate voltage for two [...]
MOSFET Compact Modeling Issues for Low Temperature (77 K – 200 K) Operation
Advanced compact models are evaluated for simulation of mixed analog-digital circuits working at low temperature (77 to 200 K). This evaluation is performed on a dual gate oxide CMOS technology with 0.18 µm / 1.8 [...]
Interface-trap Charges on Recombination DC Current-Voltage Characteristics in MOS transistors
The interface traps and trapped charges along the surface channel region are generated during transistor stress or operation and primarily responsible for the changes of device properties. The threshold voltage is varied by the generation [...]
Compact Analytical Threshold Voltage Model for Nanoscale Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) MOSFET
In this paper, compact analytical threshold voltage model for multi-layered-gate electrode workfunction engineered recessed channel (MLGEWE-RC) MOSFET is presented and investigated using ATLAS device simulator. The novel device continues merits of recessed channel and dual [...]
Compact Model of the Ballistic Subthreshold Current in Independent Double-Gate MOSFETs
Double-Gate structures with independent gates have been recently proposed, allowing a four terminal operation. Independent Double-Gate (IDG) MOSFETs offer additional potentialities, such as a dynamic threshold voltage control by one of the two gates, transconductance [...]
A Technique for Constructing RTS Noise Model Based on Statistical Analysis
In this paper, a technique for constructing the RTS noise model based on the statistical analysis of the noise data obtained from the Schottky diode under different biases is introduced. The three RTS parameters: pulse [...]
Impact of Non-Uniformly Doped and Multilayered Asymmetric Gate Stack Design on Device Characteristics of Surrounding Gate MOSFETs
In the present work, a new structural concept, non-uniformly doped multilayered asymmetric gate stack (ND-MAG) surrounding gate MOSFET has been proposed and it has been demonstrated using analytical modeling and simulation that ND-MAG SGT leads [...]
HiSIM-HV: a complete surface-potential-based MOSFET model for High Voltage Applications
Oritsuki Y., Yokomiti M., Sakuda T., Sadachika N., Miyake M., Kajiwara T., Feldmann U., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Hiroshima University, JP
We present here the high-voltage MOSFET model HiSIM-HV based on the complete surface-potential description. The model is valid both for symmetrical and asymmetrical structures with scaling properties for any structural variations valid for wide range [...]
Si-Based Process Aware SPICE Models for Statistical Circuit Analysis
Krishnamurthy S., Dasarapu V.K., Mahotin Y., Ryles R., Roger F., Uppal S., Mukherjee P., Cuthbertson A., Lin X-W, Synopsys, Inc., US
This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parametersfrom silicon data. The robustness of this methodology was tested [...]
Journal: TechConnect Briefs
Volume: 3, Nanotechnology 2008: Microsystems, Photonics, Sensors, Fluidics, Modeling, and Simulation – Technical Proceedings of the 2008 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: June 1, 2008
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 978-1-4200-8505-1