Papers:
Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack
Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leady MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on [...]
A Basic Property of MOS Transistors and its Circuit Implications
The MOS transistor drain current is the (linear) superposition of independent and symmetrical effects of source and drain voltages. This basic property is not affected by the geometry or symmetry of the transistor, by the [...]
USIM Design Considerations
Compact models need to be carefully designed to predict circuit behavior efficiently, accurately and robustly. A variety of effects must work together and be consistently integrated into the model equations with redundancy. USIM is a [...]
Theory, Development and Applications of the Advanced Compact MOSFET (ACM) Model
Galup-Montoro C., Schneider M.C., Cunha A.I.A., Gouveia-Filho O.C., Universidade Federal de Santa Catarina, BR
This paper presents a physics-based advanced compact MOSFET (ACM) model. The ACM model is composed of very simple expressions, valid for any inversion level, conserves charge and preserves the source-drain symmetry of the transistor. We [...]
HiSIM: Accurate Charge Modeling Important for RF Era
Miura-Mattausch M., Navarro D., Ueno H., Mattausch H.J., Miura-Mattausch M., Morikawa K., Itoh S., Kobayashi A., Masuda H., Hiroshima University, JP
Extension of the gradual-channel approximation is presented with the surface-potential-based MOSFET modeling. All phenomena observed under the saturation condition are described by the potential increase in the pinch-off region in a self-consistent way. The charge [...]
An Advanced Surface-Potential-Plus MOSFET Model
Like other surface-potential based model, our surface-potential-plus model starts with charge-sheet approximation, uses the quasi-Fermi-potential to integrate drift and diffusion current and formulates an inversion charge equation that can be analytically solved for given terminal [...]
A Technology-based Compact Model for Predictive Deep-Submicron MOSFET Modeling and Characterization
This paper presents new development results of our compact model (Xsim) for deep-submicron MOSFETs. Although a threshold-voltage-based and source-referenced regional model, Xsim meets the basic requirements of continuity (to third-order derivatives), scalability (entire geometry range), [...]
A Framework for Generic Physics Based Double-Gate MOSFET Modeling
Chan M., Taur Y., Lin C.H., He J., Niknejad A., Hu C., Hong Kong University of Science & Technology, HK
This paper presents a framework to develop a generic and physical Double-Gate MOSFET model. Due to limited available physical data and existence of a large variety of device structures, flexibility to assemble model modules to [...]
A Physics-Based Compact Model for Nano-Scale DG and FD/SOI MOSFETs
A process/physics-based compact model (UFDG) for double-gate (DG) MOSFETs is overviewed. The model, in essence, is a compact Poisson-Schrödinger solver, including accountings for short-channel effects, and is applicable to nano-scale fully depleted (FD) SOI MOSFETs [...]
BJT Modeling with VBIC, Basics and V1.3 Updates
This paper reviews the VBIC BJT model, and details updates in the version 1.3 release. VBICv1.3 includes explicit interaction with siulator global parameters gmin and pnjmaxi, explicit limiting of local temperature rise and exponential arguments [...]
Compact Bipolar Transistor Modeling – Issues and possible solutions
Recently, several advanced compact bipolar transistor models ave become available to the design community. For existing technologies, these models (and their internal formulation) are believed to offer sufficient flexibility and accuracy, especially compared to the [...]
Noise Modeling with MOS Model 11 for RF-CMOS Applications
Scholten A.J., Tiemeijer L.F., van Langevelde R., Zegers-van Duijnhoven A.T.A., Havens R.J., Zegers-van Duijnhoven A.T.A., Venezia V.C., Klaassen D., Philips Research Laboratories Eindhoven, NE
The RF noise in 0.18um CMOS technology has been measured and modeled. Compared to long-channel theory we find only a moderate enhancement of the drain and current noise for short-channel MOSFETS and, due to the [...]
Physical Modeling of Substrate Resistance in RF MOSFETs
A simple and accurate method is presented for extracting the substrate resistance of RF MOSFETs. The extraction results for 0.18 um MOSFETs are shown for various bias conditions. The dependence of the extracted substrate resistances [...]
Compact Modeling for RF and Microwave Integrated Circuits
Niknejad A.M., Chan M., Hu C., Brodersen B., Xi J., He J., Emami S., Doan C., Cao Y., Su P., Wan H., Dunga M., Lin C.H., University of California at Berkeley, US
Compact modeling has been an integral part of the design of integrated circuits for digital and analog applications. The availability of scalable CMOS device models has enabled rapid simulation and design of present and future [...]
Vector Potential Equivalent Circuit for Efficient Modeling of Interconnect Inductance
We present a compact topology for inductive parasitics, using the vector potential as a state variable. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range [...]
A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET’s Operation from the Accumulation to Depletion Region
A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFETs Operation from Strong Accumulation to Depletion region Jin He*+, Xuemei Xi*, Mansun Chan*, and Chenming Hu* (*Electronics Research Laboratory, Department of Electrical Engineering and Computer [...]
Modeling of Direct Tunneling Current in Multi-Layer Gate Stacks
Dunga M.V., Xi X., He J., Polishchuk I., Lu Q., Chan M., Niknejad A., Hu C., University of California-Berkeley, US
Device scaling to improve performance calls for reduction of the gate oxide thickness but at a cost of increased direct tunneling gate current. The ITRS 2001 recognizes the need of gate scaling below 2nm and [...]
Substrate Current in Surface-Potential-Based Compact MOSFET Models
A new substrate current model was developed which retains the simplicity of the original one but is applicable to all regions of the MOSFET operation with asymtotically correct behaviors and is well suited for use [...]
Application of Genetic Algorithm to Compact Model Parameter Extraction
The total number of model parameters in compact MOSFET models is usually between 50 and 300, necessitating an elaborate extraction process. Gradient-based optimization techniques were found to be useful but somewhat limited in their scope. [...]
A Surface-Potential-Based Compact Model of NMOSFET Gate Tunneling Current
Gu X., Wang H., Gildenblat G., Workman G., Veeraraghavan S., Shapira S., Stiles K., Penn State University, US
The continued aggressive scaling of the gate oxide thickness makes the accurate modeling of the gate tunneling current an important aspect of the MOSFET compact model. This work presents a new compact model of which [...]
Gate Current Partitioning in MOSFET Models for Circuit Simulation
Ngo Q., Navarro D., Mizoguchi T., Hosakawa S., Ueno H., Miura-Mattausch M., Yang C.Y., Santa Clara University, US
Gate current plays a critical role in circuits featuring sub-100nm MOSFETs. This paper elucidates the importance of gate current partitioning for accurate circuit simulation. Past publications have presented gate current models based on surface potential [...]
Double-Gate CMOS Evaluation for 45nm Technology Node
Interest in the double-gate (DG) MOSFET has been growing as transistor development is approaching the end of SIA roadmap. Recent progress in DG technology, and some theoretical study have promoted DG to one of the [...]
Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode
Recently, a double-gate structure has attracted much attention as an emerging device concept. The DG MOSFET is regarded as the most scalable device. Usually the DG MOSFET is supposed to be used as a three-terminal [...]
A Compact Model Methodology for Device Design Uncertainty
Todays ULSI chip and transistor technologies have a high degree of concurrency due to the complexity of new, advanced high performance features. This creates challenges for circuit designer who must account for the evolution of [...]
Unified Length-/Width-Dependent Threshold Voltage Model with Reverse Short-Channel and Inverse Narrow-Width Effects
The objective of this work is to develop a unified geometry-dependent scalable threshold voltage (Vt) model for the entire range of drawn length (L) and drawn width (W) without binning, including reverse short-channel effect (RSCE) [...]
Unified Length-/Width-Dependent Drain Current Model for Deep-Submicron MOSFETs
The motivation of this work is to develop a unified geometry-dependent drain current (Ids) model for the entire range of drawn length (L) and drawn width (W) without binning, considering all important short-/narrow-channel effects including [...]
An Interactive Website as a Tool for CAD of Power Circuits
The rapid development of microelectronics results in more complex semiconductor device structures and makes it necessary to use modern computer software. However, high prices and hardware requirements considerably limit the access to these CAD tools [...]
Multidimensional Model-Based Parameter Estimation Method for Compact Modeling of High-Speed Interconnects
A new multivariate modeling technology is developed that allows engineers to define the frequency range, layout parameters, material properties and desired accuracy for automatic generation of simulation models of general passive electrical structures. It combines [...]
An Automatic Macro Program developed for Characterization, Parameter Extraction and Statistic Analysis of Spiral Inductors
In the paper, a macro program based on Agilent IC-CAP software is developed for characterization, parameter extraction and statistic analysis of on chip spiral inductors. All procedures can be finished very easily in few buttons [...]
Unified RLC Model for On-Chip Interconnects
We present a unified RLC model for deep sub-micron on-chip interconnects. The model consists of two components, a quasi-3D capacitance extraction based on a novel concept of "effective width" and a effective loop inductance model. [...]
Compact Modling of High Frequency Phenomena for On-Chip Spiral Inductors
This paper presents a physics-based compact model for predicting high frequency performance of spiral inductors. The model accurately accounts for skin effect and proximity effect in the metal conductors as well as eddy current loss [...]
A Surface-Potential-Based Extrinsic Compact MOSFET Model
Gu X., Gildenblat G., Workman G., Veeraraghavan S., Shapira S., Stiles K., Pennsylvania State University, US
This work presents the extrinsic part of a recently developed advanced surface-potential-based compact MOSFET model (SP). At present, it includes a novel engineering gate current model, a substrate current model valid in all regions of [...]
A Unified Environment for the Modeling of Ultra Deep Submicron MOS Transistors
This paper discusses the aspects of modern MOS modeling requirements. Starting fro the fact, that even the Compact Model Council (CMC) outlined BSIM3v3 as a standard MOS simulation mode, many other models are used throughout [...]
Standardization of Compact Device moding in High Level Description Language
This paper proposes a methodology based on hardware description languages (HDL) to efficiently develop compact device models. After an introduction to compact device modeling we describe Verilog-AMS, a popular HDL. Then we show how Verilog-AMS [...]
Changing the Paradigm for Compact Model Integration in Circuit Simulators Using Verilog-A
Verilog-A has been demonstrated to be a suitable language to describe analog models. However, effective adoption by both the Electronic Design Automation (EDA) industry and end users requires that the language implementation provide all of [...]
Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Published: February 23, 2003
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 0-9728422-1-7