Verilog-A has been demonstrated to be a suitable language to describe analog models. However, effective adoption by both the Electronic Design Automation (EDA) industry and end users requires that the language implementation provide all of the features and performance of C-coded models. A new architecture is proposed for implementing Verilog-A models in contemporary commercial simulators. The key components of the architecture are a stand-alone compiler that generates a dynamically linkable library and a run-time environment that is customized to particular simulators. In this paper we present simulation results using this architecture implemented in several simulators. We use industrial standard models, including BSIM3 and BSIM4, as a demonstration of complex models implemented in Verilog-A.
Journal: TechConnect Briefs
Volume: 2, Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show, Volume 2
Published: February 23, 2003
Pages: 376 - 379
Industry sector: Sensors, MEMS, Electronics
Topics: Compact Modeling