FinFET – Page 2 – TechConnect Briefs

Discreteness and Distribution of Drain Currents in FinFETs

Lu N., IBM, US

It is likely that the characterization and modeling of a finFET will be carried out on a multi-fin structure, since it is a single electrical device functionally. Discreteness of multiple fins in a multi-fin FET [...]

Modeling of Dynamic Threshold Voltage of High K Gate Stack and Application in FinFET Reliability

He H., He J., Ma C., Wang C., Zhang A., He H., He J., Peking Univeristy, CN

A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model [...]

Compact Models for sub-22nm MOSFETs

Chauhan Y.S., Lu D., Venugopalan S., Morshed T., Karim M.A., Niknejad A., Hu C., University of California-Berkeley, US

FinFET and UTBSOI FET (or ETSOI) are the two promising multi-gate FET candidates for sub-22nm CMOS technology. BSIM multi-gate FET models (BSIM-CMG and BSIM-IMG) are the surface potential based physical compact models for FinFET and [...]

FinFET reliability issue analysis by forward gated-diode method

Liu Z., PKU HKUST Shenzhen Institution of IER., CN

The reliability issue of the FinFET device is studied in details in this paper by the forward gated-diode R-G current method. Extraction of the stress induced interface states and oxide traps of FINFET is performed [...]

Subthreshold Quantum Ballistic Current and Quantum Threshold Voltage Modeling for Nanoscale FinFET

Monga U., Fjeldly T.A., UniK/Norwegian University of Science and Technology, NO

A subthreshold quantum ballistic current model and a quantum threshold voltage model is presented for nanoscale FinFET.The eigenvalues are determined by solving Schrödinger equation along the gate-to-gate axis. The current is then modeled using Natori’s [...]

1/f Noise Model for Double-Gate FinFET Biased in Weak Inversion

Wei C.Q., Xiong Y.Z., Zhou X., Nanyang Technological University, SG

1/f noise model of long channel lightly-doped FinFET biased in weak inversion has been described using Hooge’s theory. From the drain current equation and the channel conductance expression, the total number of carriers under the [...]

Compact Modeling of Dynamic Threshold Voltage of FinFET High K Gate Stack and Application in Circuit Simulation

He F., Ma C., Li B., Lin X., Zhang L., Zhang X., Zhang L., Zhang X., Lin X., SZPKU, CN

Compact modeling study of dynamic threshold voltage of FinFET high K gate stack is proposed in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this [...]

A Unified Compact model for FinFET and Silicon Nanowire MOSFETs

Zhu G.J., Zhou X., See G.H., Lin S-H, Wei C.Q., Zhang J.B., Nanyang Technological University, SG

A unified compact model for FinFET and Silicon Nanowire (SiNW) MOSFETs including all major short channel effects is presented. Source-Drain symmetry, which is a fundamental feature of an ideal MOSFET, is preserved. The unified compact [...]

A PSP based scalable compact FinFET model

Smit G.D.J., Scholten A.J., Serra N., Pijper R.M.T., van Langevelde R., Mercha A., Gildenblat G., Klaassen D.B.M., NXP Semiconductors, NL

A high-quality compact FinFET model is a prerequisite for initial circuit design and evaluation of these prospective replacements for conventional bulk MOSFETs. Our PSP-based compact model for symmetric 3-terminal FinFETs with thin undoped or lightly [...]

A Versatile Multigate MOSFET Compact Model: BSIM-MG

Hu C., Dunga M., Lin C.H., Lu D., Niknejad A., University of California-Berkeley, US

BSIM-MG is a surface-potential based compact model for multi-gate MOSFETs such as FinFETs fabricated on either SOI or bulk substrates. It can model transistors with the gate controlling two, three, or four sides of the [...]