Chauhan Y.S. – TechConnect Briefs

Unified Compact Model for Gate All Around FETs- Nanosheets, Nanowires, Multi Bridge Channel MOSFETs

Kushwaha P., Duarte J.P., Lin Y-K., Agarwal H., Chang H-L, Sachid A., Salahuddin S., Chauhan Y.S., Hu C., University of California Berkeley USA, US

FinFET is in mass production for its capability of scaling below 20nm. Thin silicon Fin surrounded by gate provides a superior channel electrostatics resulting in higher on current (Ion) and better subthreshold swing. The same [...]

ASM-HEMT: Industry Standard GaN HEMT Model for Power and RF Applications

Ghosh S., Ahsan S.A., Khandelwal S., Pampori A., Dangi R., Chauhan Y.S., IIT Kanpur, IN

HEMTs based on GaN have become immensely ubiquitous in the past decade and offer a strong competition to mature technologies like silicon primarily due to the superior characteristics offered by the GaN material system over [...]

Modeling Independent Multi-Gate MOSFET

Duarte J.P., Khandelwal S., Chang H-L, Chauhan Y.S., Hu C., University of California-Berkeley, US

In this paper a fully-featured turn-key compact model for independent multi-gate MOSFETs is presented. This industry standard compact model is called BSIM-IMG. The two independent (front- and back-gate) control of the channel charge in these [...]

InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG

Khandelwal S., Duarte J.P., Paydavosi N., Chauhan Y.S., Gu J.J., Si M., Ye P.D., Hu C., University of California-Berkeley, US

In this paper, we present modeling results for InGaAs FinFETs using the industry standard compact model BSIM-CMG. We show that BSIM-CMG produces excellent fits to the measured I-V data of these devices. The difference seen [...]

Analytical Surface Potential Calculation in UTBSOI MOSFET with Independent Back-Gate Control

Khandelwal S., Chauhan Y.S., Karim M.A., Venugopalan S., Sachid A., Niknejad A., Hu C., Norwegian University of Science & Technlogy, NO

An analytical method for calculation of front- and back-gate surface-potential in ultra-thin body SOI MOSFETs is presented. The method allows surface-potential calculation with independent back-gate control which is very important in these devices. The calculated [...]

BSIM6: Symmetric Bulk MOSFET Model

Chauhan Y.S., Karim M.A., Venugopalan S., Khandelwal S., Niknejad A., Hu C., University of California-Berkeley, US

BSIM6 Model is the next generation Bulk RF MOSFET Model. Model uses charge based core with all physical models adapted from BSIM4 model. Model fulfills all quality tests e.g. Gummel symmetry and AC symmetry etc. [...]

Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs

Karim M.A., Venugopalan S., Chauhan Y.S., Lu D., Niknejad A., Hu C., University of California at Berkeley, US

MOSFET intrinsic capacitances going negative is a major concern in the compact model community. Negative Intrinsic Capacitances (NIC) can raise non-convergence issues in circuit simulators. In some cases NICs can be explained using physical phenomena. [...]

Compact Models for sub-22nm MOSFETs

Chauhan Y.S., Lu D., Venugopalan S., Morshed T., Karim M.A., Niknejad A., Hu C., University of California-Berkeley, US

FinFET and UTBSOI FET (or ETSOI) are the two promising multi-gate FET candidates for sub-22nm CMOS technology. BSIM multi-gate FET models (BSIM-CMG and BSIM-IMG) are the surface potential based physical compact models for FinFET and [...]