Bipolar MOSFETs with a pure base and two MOS gates usually have electrically short channels compared with its intrinsic Debye length of about 25μm at room temperatures. This short channel effect was missed by all [...]
This paper presents a physics-based non-charge-sheet analytic model for an ideal retrograde doping MOSFET structure. The model adopts an approach of solving Poisson’s equation for the heavily-doped region and lightly-doped region, respectively, and the analytic [...]
Gate Induced Drain Leakage (GIDL) current is one of the most important leakage components in Silicon-on-Insulator (SOI) MOSFET devices. The effect of GIDL current reported before mainly focused on device characteristics in the OFF-state or [...]
The gate leakage, floating body effect, and history effect in 32nm HKMG PD-SOI CMOS have been extensively studied and analyzed. Based on the measured data, a comprehensive HKMG PD-SOI gate leakage model has been developed [...]
A unified charge-based model for SOI MOSFETs is presented. The proposed model is valid and accurate from intrinsic to heavily doped channel with various structure parameter variations. The framework starts from one-dimension Poisson-Boltzmann’s equation. Based [...]
A subthreshold quantum ballistic current model and a quantum threshold voltage model is presented for nanoscale FinFET.The eigenvalues are determined by solving Schrödinger equation along the gate-to-gate axis. The current is then modeled using Natori’s [...]
The analytical symmetric and asymmetric lightly doped DG-MOSFET device electrostatic potential compact model presented here improves the compact model accuracy without any iteration. The model is developed using the Lambert Function and a 2-dimensional (2-D) [...]
This paper presents an analytic channel potential solution of the symmetrical DG AMOSFETs. The proposed solution is derived from complete 1-D Poisson-Boltzmann equation by taking three components of net charge density (fixed charge, holes and [...]
A compact model for four terminal double-gate MOSFET, based on double charge-sheet approximation with carrier velocity saturation, is discussed. Although it is a monolithic model both for conductance and intrinsic capacitances, it is not a [...]
, Lin S-H
, Selvakumar R.
, Srikanth M.K.
, Wei C.Q.
, Yan Y.F.
, Zhang J.B.
, Zhou X.
, Zhu G.J.
, Nanyang Technological University, SG
This paper presents benchmark tests of the unified compact model (Xsim) for double-gate (DG) and gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs, which has been developed over the years with the unified regional modeling (URM) approach. The [...]
An analytical model is presented for the 3-D electrostatics of lightly doped GAA square gate MOSFETs operating in the subthreshold domain. The model is based on the assumption of parabolic potential distributions in the directions [...]
A continuous and explicit compact model of short-channel effects (SCEs) for undoped cylindrical Gate-All-Around (GAA) MOSFETs is presented in this paper. SCEs are implemented into an analytic and continuous drain-current model based on a surface [...]
Surrounding-Gate MOS transistors are seen as viable slternative to the problems of bulk MOSFET in deep sub-micron region. However modeling of drain current and capacitances, like other MOS structures require solution of an implicit equation. [...]
The particular shape of Gate-All-Around (GAA) nanowires allows a much higher electrostatic control of the active region than conventional devices, as required for the integration at the end-of-roadmap. This architecture is suitable for ultra-scaled devices [...]
The bias dependence of low frequency noise (LFN) is investigated with measurements in 90nm CMOS. A recent charge-based LFN model combining carrier and mobility fluctuation components is compared to data from multi-finger devices with a [...]
In this paper, compact models for transient response of dispersionless interconnects are rigorously derived with resistive, inductive and capacitive terminal loads. The proposed compact models are verified by the HSPICE simulation with high accuracy and [...]
Compact models for quantum mechanical behavior of transistors are becoming increasingly important as shrinking transistor sizes bring the oxide thickness to below four nanometers. An exponential approximation for the silicon potential is used to derive [...]
For analog circuit designers, both reducing device mismatch and having a good device mismatch model are very important. Pelgrom characterized device mismatch between two devices separated by a finite distance D as sqrt[a^2/(W*L) + b^2*D^2]. [...]
Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for both simulation and synthesis (IEEE1364-2001 and [...]
Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2010: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational
Published: June 21, 2010
Industry sector: Sensors, MEMS, Electronics
Topics: Compact Modeling