Papers:
A Physics Based Approach to Compact Modeling of Noise in Modern Bipolar Transistors
A physics based approach to compact modeling of bipolar transistor noise is described. Frequency dependent intrinsic base current noise, its correlation to intrinsic collector current noise, avalanche of intrinsic collector current noise entering the collector-base [...]
Modeling Independent Multi-Gate MOSFET
In this paper a fully-featured turn-key compact model for independent multi-gate MOSFETs is presented. This industry standard compact model is called BSIM-IMG. The two independent (front- and back-gate) control of the channel charge in these [...]
Compact modeling for UTBB-FDSOI technologies: Main challenges and possible solutions
Fully-Depleted Silicon-On-Insulator (FDSOI) technologies featuring Ultra-Thin silicon Body and Buried oxide (UTBB) have now entered into industrial production stage. These technologies present several decisive advantages over other options, such as excellent transistor electrostatic control, very [...]
New Elements and Features in the Process Design Kits for a FinFET Technology
Lu N., Baizley A., Guan X., Johnson J., McCullen J., Ozbek A., Rahman A., Wang H., Yu M., Zemke C., Rausch W., Wachnik R., IBM, US
Parasitic resistance is a primary performance constraint in FinFET technologies. We report that new and innovative elements and features have been introduced into Process Design Kits for 14nm FinFET technology. They enable accurate and efficient [...]
Reliability-Aware Device Modeling and Implications on Circuit Aging Simulations
Device reliability and circuit aging are becoming key design concerns with advanced CMOS technologies. In the traditional way, a reliability model describing the device parameter shifts in the time domain is independent of a device [...]
Compact Modeling of Long-Term MOSFET Degradation for Predicting Circuits Degradation
Miyamoto H., Ma C., Mattausch H.J., Miura-Mattausch M., Tanoue H., Tanimoto Y., Kikuchihara H., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Hiroshima University, JP
[Introduction] Prediction methods of long-term degradation of both p- and n-type metal oxide semiconductor field effect transistors (MOSFETs) in CMOS circuits is proposed. During CMOS circuit degradation, not all the MOSFETs but only several MOSFETs [...]
SPICE Compact Modeling for Design of Innovative Integrated Circuits in CEA-LETI
This paper presents an overview of the recent compact modeling activity in CEA-LETI. Examples of Verilog-A modeling using the surface potential approach of field effect transistors, such as High Electron Mobility Transistors (HEMTs) AlGaN/GaN power [...]
A Hybrid Process Design Kit: Towards Integrating CMOS and III-V Devices
Chiah S.B., Zhou X., Lee K.E.K., Ng C.Y., Antoniadis D., Fitzgerald E.A., Nanyang Technological University, SG
A hybrid process design kit (PDK) for novel integrated circuits incorporating high performance compound semiconductor materials and devices into existing production Si-CMOS compatible foundry process is presented. The hybrid PDK permits direct integration of Au-free [...]
Journal: TechConnect Briefs
Volume: 4, Advanced Manufacturing, Electronics and Microsystems: TechConnect Briefs 2016
Published: May 22, 2016
Industry sector: Sensors, MEMS, Electronics
Topic: WCM - Compact Modeling
ISBN: 978-0-9975-1173-4