Papers:
A novel simulation methodology for full chip-package thermo-mechanical reliability investigations
Karunamurthy B., Ostermann T., Bhattacharya M., KAI Kompetenzzentrum Automobil- und Industrieelektronik GmbH, AT
A methodology for simulating the accurate structural details of a non-planarized technology chips is presented. This approach uses a virtual semiconductor fabrication technique to create geometry and finite element mesh on complex chip topology features. [...]
Methodology and tool support for micro- and nano product engineering for SMEs
The development of micro and nano tech devices such as MEMS (micro-electro-mechanical systems) and NEMS (nano-electro-mechanical systems) based on semiconductor manufacturing processes comprises the structural design as well as the definition of the manufacturing process [...]
Simulation of Back-Electrode Effects on Lags and Current Collapse in Field-Plate AlGaN/GaN HEMTs
Two-dimensional transient analysis of gate-field-plate AlGaN/GaN high electron mobility transistors with a backside electrode is performed by considering a deep donor and a deep acceptor in a buffer layer. Effects of introducing a field plate [...]
Current-Controlled Switches for HV SoI Processes – Structure, Application and Integration in Functional Blocks
The paper presents an approach to high-voltage current-controlled switches, their structures, properties and application possibilities. Moreover, ways of merging these switches into core structure of HV processing components, so as to retain required switch operation [...]
Electronic properties in two dimensional quantum rings consisting of two nanoelements
Electron spectrum and ground state properties in two dimensional confined quantum rings with R(1,2) radiuses (R1 les R2), consisting of the two different (material) nanoelements divided by two sectored finite size quantum wells with various [...]
Analytic Model forAmorphous GST OTS in Phase Change Memory Cell with Hopping Transport
Wang C., Wang H., Wang W., Wang C., Wang H., Wang W., Cao Y., Wang C., Wang H., Wang W., Ye Y., He J., PKU-HKUST Shenzhen-Hongkong Institution, CN
This paper presents an analytic model for amorphous GST OTS in phase-change-memory cell with the hopping transport mechanism, which is widely used in the organic semiconductor device simulation. In this work an equivalent hopping probability [...]
Numerical Study on Gate-All-Around Tunneling FET with SiO2 Core and Si Shell Structure
Zhang A., Zhang L., Zhang X., Zhang A., Zhang L., Zhang X., Mei J., Zhang A., Zhang L., Zhang X., He H., He J., He H., He J., Chan M., PKU-HKUST Shenzhen-Hongkong Institution, CN
This work presents a gate-all-around tunneling FET based on SiO2 core and Si shell structure (GAA-SOI-TFET) and demonstrates its performance characteristics via the numerical simulation method. The 3-D T-CAD numerical simulations demonstrate that this new [...]
Junctionless Nanowire MOSFET with Dynamic Threshold Voltage Operation Methodology
Mei J., Zhang A., Yu C., Ye Y., Wang H., Deng W., He J., PKU-HKUST Shenzhen-Hongkong Institution, CN
In this paper, a junctionless nanowire MOSFET with the dynamic threshold voltage operation methodology (DT-JNT) is proposed and its characteristics are studied comparing with those of a conventional junctionless nanowire transistor (JNT) and a double-gate [...]
Thermal Coupling in Technologies Based on Tri-gate Transistors
This paper presents the analyses of static and dynamic thermal coupling among microsystem components for technologies based on tri-gate transistors. Simulations were carried out using Green’s function thermal solver based on power trace data computed [...]
Optimized Topology of an ASIC for Thermal Analysis of Multi-Core Processors
The main goal of the paper is to present the optimized ASIC design for the investigation of thermal-coupling among cores in multi-core processors. In short, we designed a dedicated ASIC composed of regular 16x24 heat [...]
Current-mode Processing Possibilities in HV SoI Integrated Systems
The paper discusses possibilities of current-mode based functional block implementation into signal path of HV SoI voltage-mode circuits. The topic arose as an effect of research on HV SoI ASICs for automotive applications. It turned [...]
Integration of memristors with MEMS in different circuit configurations
The detailed simulation of the recently proposed MEMS-memristor integration is presented. Interestingly, charge transfer is an operating principle that is common to both memristors and certain kinds of MEMS devices such as parallel plate capacitors. [...]
A simulation study on the property of micro-arrayed negative refractive index material for the energy transfer
In this paper we discuss in building a micro-arrayed negative refractive index material which enhances the energy transfer between a wireless transmitter and a receiver. We simulate and study the effects of introduction of negative [...]
The Effects of Dwell_time of Monopolar Waveform on Droplet Formation through the Analysis of Fluid Propagation Direction
For inkjet printing, the fluid dynamics in a capillary tube caused by the movement of the piezoelectric material is essential due to the need to adjust the voltage pulse waveform, but it has seldom been [...]
An Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements
We present a schematic transistor model for multi-finger multi-fin FETs, which reduces an initial complex finFET network to a very simple finFET network. The schematic finFET model is accurate in predicting overall finFET characteristics, including [...]
Compact Modeling of Parameter Variations of Nanoscale CMOS due to Random Dopant Fluctuation
Ye Y., Zhu Y., He H., He J., Mei J., Cao Y., He H., He J., PKU-HKUST Shenzhen-Hongkong Institution, CN
In nanoscale CMOS design, the compact modeling of random dopant fluctuation (RDF), which is the major variability source, is crucial important to bridge the variation aware design to the underlying physics. In this paper the [...]
GIDL Current and Pass-Gate Body Potential Modeling in 22nm HKMG PD-SOI CMOS
In a floating PD (partially depleted) SOI (silicon-on-insulator) transistor, the internal DC body potential is determined by the various body current components, mainly including diode current, gate-to-body oxide tunneling current (Igb), impact ionization current (II) [...]
Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2013: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational (Volume 2)
Published: May 12, 2013
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Informatics, Modeling & Simulation
ISBN: 978-1-4822-0584-8