Mei J. – TechConnect Briefs

Application of Multi-frequency Test and Neural Network to Fault Diagnosis in Analog Circuits

Chan M., He J., Liang H-L, Mei J., Wang C., Wang H., Ye Y., PKU-HKUST Shenzhen-Hongkong Institution, CN

In this paper, the multi-frequency test and neural networks (NNs) are applied to fault diagnosis in analog circuits. The reason is that multi-frequency test can maximize differences between the failure and the normal circuit’s response, [...]

Compact Modeling of Parameter Variations of Nanoscale CMOS due to Random Dopant Fluctuation

Cao Y., He H., He J., Mei J., Ye Y., Zhu Y., PKU-HKUST Shenzhen-Hongkong Institution, CN

In nanoscale CMOS design, the compact modeling of random dopant fluctuation (RDF), which is the major variability source, is crucial important to bridge the variation aware design to the underlying physics. In this paper the [...]

Junctionless Nanowire MOSFET with Dynamic Threshold Voltage Operation Methodology

Deng W., He J., Mei J., Wang H., Ye Y., Yu C., Zhang A., PKU-HKUST Shenzhen-Hongkong Institution, CN

In this paper, a junctionless nanowire MOSFET with the dynamic threshold voltage operation methodology （DT-JNT） is proposed and its characteristics are studied comparing with those of a conventional junctionless nanowire transistor (JNT) and a double-gate [...]

Numerical Study on Gate-All-Around Tunneling FET with SiO2 Core and Si Shell Structure

Chan M., He H., He J., Mei J., Zhang A., Zhang L., Zhang X., PKU-HKUST Shenzhen-Hongkong Institution, CN

This work presents a gate-all-around tunneling FET based on SiO2 core and Si shell structure (GAA-SOI-TFET) and demonstrates its performance characteristics via the numerical simulation method. The 3-D T-CAD numerical simulations demonstrate that this new [...]