Numerical Study on Gate-All-Around Tunneling FET with SiO2 Core and Si Shell Structure

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This work presents a gate-all-around tunneling FET based on SiO2 core and Si shell structure (GAA-SOI-TFET) and demonstrates its performance characteristics via the numerical simulation method. The 3-D T-CAD numerical simulations demonstrate that this new device has steep subthreshold swing (<60mV/dec), suppressed drain-induced barrier lowering, and enhanced Ion/Ioff ratio up to 109 orders of magnitude. It is worth noting that Ion begins to increase when SiO2 core radius exceeds a specified value (~4nm) while influence of gate oxide thickness on the device performance being an important factor.

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Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2013: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational (Volume 2)
Published: May 12, 2013
Pages: 512 - 515
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Informatics, Modeling & Simulation
ISBN: 978-1-4822-0584-8