Optimized Topology of an ASIC for Thermal Analysis of Multi-Core Processors

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The main goal of the paper is to present the optimized ASIC design for the investigation of thermal-coupling among cores in multi-core processors. In short, we designed a dedicated ASIC composed of regular 16×24 heat cell array. The power dissipation in each cell is configurable in a wide range. Therefore, it can be used to emulate the power dissipation in the units of a multi-core processor and produce the resulting temperature distribution in a chip. Due to its flexible structure, the described ASIC allows the investigation of any core topology and fabricated in modern nanometer technologies. For example, it can be used to predict the thermal behavior of 16-core processor fabricated using 16 nm process.

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Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2013: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational (Volume 2)
Published: May 12, 2013
Pages: 524 - 527
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Informatics, Modeling & Simulation
ISBN: 978-1-4822-0584-8