Papers – TechConnect Briefs

A Hybrid Process Design Kit: Towards Integrating CMOS and III-V Devices

Antoniadis D., Chiah S.B., Fitzgerald E.A., Lee K.E.K., Ng C.Y., Zhou X., Nanyang Technological University, SG

A hybrid process design kit (PDK) for novel integrated circuits incorporating high performance compound semiconductor materials and devices into existing production Si-CMOS compatible foundry process is presented. The hybrid PDK permits direct integration of Au-free [...]

SPICE Compact Modeling for Design of Innovative Integrated Circuits in CEA-LETI

Barbe J.-C., Lucci L., Martin P., Reyboz M., CEA-LETI, FR

This paper presents an overview of the recent compact modeling activity in CEA-LETI. Examples of Verilog-A modeling using the surface potential approach of field effect transistors, such as High Electron Mobility Transistors (HEMTs) AlGaN/GaN power [...]

Compact Modeling of Long-Term MOSFET Degradation for Predicting Circuits Degradation

Kikuchihara H., Ma C., Mattausch H.J., Miura-Mattausch M., Miyamoto H., Tanimoto Y., Tanoue H., Hiroshima University, JP

[Introduction] Prediction methods of long-term degradation of both p- and n-type metal oxide semiconductor field effect transistors (MOSFETs) in CMOS circuits is proposed. During CMOS circuit degradation, not all the MOSFETs but only several MOSFETs [...]

Reliability-Aware Device Modeling and Implications on Circuit Aging Simulations

Chan M., Ma C., Zhang L., Hong Kong University of Science and Technology, HK

Device reliability and circuit aging are becoming key design concerns with advanced CMOS technologies. In the traditional way, a reliability model describing the device parameter shifts in the time domain is independent of a device [...]

New Elements and Features in the Process Design Kits for a FinFET Technology

Baizley A., Guan X., Johnson J., Lu N., McCullen J., Ozbek A., Rahman A., Rausch W., Wachnik R., Wang H., Yu M., Zemke C., IBM, US

Parasitic resistance is a primary performance constraint in FinFET technologies. We report that new and innovative elements and features have been introduced into Process Design Kits for 14nm FinFET technology. They enable accurate and efficient [...]

Compact modeling for UTBB-FDSOI technologies: Main challenges and possible solutions

Poiroux T., CEA-LETI, FR

Fully-Depleted Silicon-On-Insulator (FDSOI) technologies featuring Ultra-Thin silicon Body and Buried oxide (UTBB) have now entered into industrial production stage. These technologies present several decisive advantages over other options, such as excellent transistor electrostatic control, very [...]

Modeling Independent Multi-Gate MOSFET

Chang H-L, Chauhan Y.S., Duarte J.P., Hu C., Khandelwal S., University of California-Berkeley, US

In this paper a fully-featured turn-key compact model for independent multi-gate MOSFETs is presented. This industry standard compact model is called BSIM-IMG. The two independent (front- and back-gate) control of the channel charge in these [...]

A Physics Based Approach to Compact Modeling of Noise in Modern Bipolar Transistors

Niu G., Auburn University, US

A physics based approach to compact modeling of bipolar transistor noise is described. Frequency dependent intrinsic base current noise, its correlation to intrinsic collector current noise, avalanche of intrinsic collector current noise entering the collector-base [...]

Applications of Silicon Nanophotonics: Space-division Multiplexing and Integrated Spectroscopy

Fainman Y., Grieco A., Hong B., Porter G., University of California San Diego, US

Data center needs are evolving as more advanced optical transmission techniques are deployed. This presentation discusses recent technological developments pertaining to the scalability and characterization of the network fabric: space-division multiplexing on a chip, and [...]

Application of Angular Method to Correct Channel Spacing Between AWG Demultiplexed Channels

Seyringer D., Vorarlberg University of Applied Sciences, AT

Arrayed Waveguide Gratings (AWGs) offer an attractive DWDM solution because they are a very compact way to provide for higher channel count solutions, have good performance characteristics, and can be more cost effective per channel [...]