Papers – Page 25 – TechConnect Briefs

R3, an Accurate JFET and 3-Terminal Diffused Resistor Model

This paper presents an improved compact model for diffused resistors and JFETs, valid over geometry, bias, and temperature. The model includes a physically based junction depletion model, a new and accurate velocity saturation model derived [...]

Modeling and Characterization of Wire Inductance for High Speed VLSI Design

Arora N.D., Song L., Cadence Design Systems, US

Ever increasing circuit density, operating speed, faster on-chip rise times, use of low resistance Copper (Cu) interconnects, and longer wire lengths due to high level of integration in VLSI chip designs, have necessitated the need [...]

Unified Regional Approach to Consistent and Symmetric DC/AC Modeling of Deep-Submicron MOSFETs

Zhou X., Chiah S.B., Chandrasekaran K., Lim K.Y., Chan L., Chandrasekaran K., Chu S., Nanyang Technological University, SG

This paper presents our new developments of Xsim, a unified regional threshold-voltage-based model for deepsubmicron MOSFETs. New features include complete reformulation with bulk reference, including transverse electric field for effective mobility resulting in source–drain symmetry, [...]

The Development of Next Generation BSIM for Sub-100nm Mixed-Signal Circuit Simulation

Xi X., He J., Heyderi B., Dunga M., Lin C.H., Heyderi B., Wan H., Chan M., Niknejad A.M., Hu C., University of California at Berkeley, US

This paper describes the next generation BSIM model for aggressively scaled CMOS technology. New features in the model include more accurate non-charge-sheet based physics, completely continuous current and derivatives, and extendibility to non-traditional CMOS based [...]

Noise Modeling with HiSIM Based on Self-Consistent Surface-Potential Description

Miura-Mattausch M., Hosokawa S., Navarro D., Matsumoto S., Ueno H., Mattausch H.J., Miura-Mattausch M., Ohguro T., Iizuka T., Taguchi M., Kage T., Miyamoto S., Hiroshima University, JP

Accurate prediction of noise characteristics is a prerequisite for RF-circuit simulation. We demonstrate here that the 1/f noise is modeled only with the trap density as a model parameter and the thermal drain noise is [...]

Recent Enhancements of MOS Model 11

van Langevelde R., Scholten A.J., Klaassen D.B.M., Philips Research Laboratories, NL

MOS Model 11 (MM11) is a surface-potential-based compact MOSFET model, which was introduced in 2001 (level 1100). An update of MM11, level 1101, was introduced in 2002. At the moment a second update of MM11, [...]

Ballistic MOS Model (BMM) Considering Full 2D Quantum Effects

Yu Z., Zhang D., Tian L., Tsinghua University, CN

As the channel length of MOSFETs is shrunk to below 50 nm, 2D quantum mechanical (QM) e®ects becomes profound on both the carrier con¯nement in the transverse direction to the channel and the carrier transport, [...]

Technology Limits and Compact Model for SiGe Scaled FETs

Dutton R.W., Choi C-H, Stanford, US

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]

Sub-Threshold Electron Mobility in SOI-MESFETs

Khan T., Vasileska D., Thornton T.J., Arizona State University, US

Micropower circuits use subthreshold MOSFETs that consume minimal power resulting from the combination of ultra-low drain currents (10-11 < Id < 10-5 A/µm) and small drain voltages required for saturation (Vd sat ~150-200mV). Unfortunately, sub-threshold [...]

Atomistic Process and Simulation in the Regime of sub-50nm Gate Length

Kwon O., Kim K., Seo J., Won T., Inha University, KR

In this paper, we report an atomistic simulation approach for sub-50nm gate length FETs. The proposed atomistic approach consists of the coupling the molecular dynamics (MD) simulations of the collision cascades for ion implantation process [...]