Papers – Page 745 – TechConnect Briefs

A Compact Model of Ballistic CNFET for Circuit Simulation

Paul B.C., Fujita S., Okajima M., Lee T., Toshiba America Research Inc., US

As silicon technology is approaching to its limit, Carbon nanotube FETs (CNFET) are shown to have potential of taking this place in the post silicon era. Consequently, interests have grown to predict the performance of [...]

Enhanced Junction Capacitance Modeling

Anderson F.G., Rassel R.M., Lavoie M.A., IBM Microelectronics, US

The current standard diode junction capacitance models do not yield high quality models for hyperabrupt junction varactors that are constructed from several implants. We describe a new enhancement that employs the actual (exponential) doping profiles [...]

A Simple Yet Accurate Mismatch Model For Circuit Simulation

Jin Z., Lee Y.M., Watts J.S., Bonaccio A.R., Schroer G.J., Pai N.G., IBM, US

As technology scales, mismatch between a pair of transistors becomes a more and more critical issue for technology development and circuit designs. Scaling also increases the complexity of compact device modeling. Sophisticated models are usually [...]

Dynamic Behavior Model for High-k MOSFETs

Dunga M.V., Xi X., Niknejad A.M., Hu C., University of California-Berkeley, US

High-K dielectrics need to be introduced into bulk CMOS to extend the scaling limits. However, the use of high-k dielectrics introduces new dynamic behavior into transistor operation. Pulsed measurements show hysteresis in drain current (Id), [...]

On Idlow with Emphasis on Speculative SPICE Modeling

Chen Q., Wu Z-Y, Icel A.B., Goo J-S, Krishnan S., Thuruthiyil C., Subba N., Suryagandh S., An J.X., Ly T., Radwin M., Yonemura J., Assad F., Advanced Micro Devices, US

An empirical correlation model of Idlow, the MOSFET drain current measured at Vgs=Vdd/2 and Vds=Vdd, where Vdd is the supply voltage, is proposed based on the alpha-power law model. It enables a comprehensive analysis of [...]

SOI CMOS Compact Modeling based on TCAD Device Simulations

Botula A., Furkay S., Sheridan D.C., Johnson J.M., Na M-H, IBM Corporation, US

This work describes a TCAD-based methodology for generating compact models for circuit design in advance of hardware availability (predictive modeling). The exercise was performed on a 65nm node SOI CMOS technology. TCAD simulations accurate enough [...]

Compact Models for Double Gate and Surrounding Gate MOSFETs

Abebe H., Cumberbatch E., Morris H., Uno S., San Jose State University, US

The models presented by Lu and Taur, [1], for lightly doped double gate and surrounding gate MOSFETs each require numerical solution of a transcendental equation. In this paper we present explicit, analytic solutions of these [...]

Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs

Kranti A., Armstrong G.A., Queen’s University of Belfast, UK

In the present paper, a compact model for short channel effects (SCEs) in source/drain engineered nanoscale DG MOSFET, is proposed for the first time and the impact of spacer width (s), lateral source/drain doping gradient [...]

Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability

Goel K., Saxena M., Gupta M., Gupta R.S., Gupta M., Gupta R.S., Professor, IN

We have modeled a new structure TRIMGAS which has 3 gate materials in the gate and an oxide stack. we have compared various parameters to see whether this strucure is superior to any of our [...]

Compact modeling and performance analysis of Double-Gate MOSFET-based circuits

Tintori O., Munteanu D., Loussier X., Autran J-L, Regnier A., Bouchakour R., L2MP, FR

Double-Gate (DG) MOS transistors and related multiple-gate device architectures are nowadays widely identified as one of the most promising solutions for meeting the roadmap requirements for the end-of-the-roadmap integration. One of the identified challenges for [...]