Papers – Page 744 – TechConnect Briefs

Fabrication and Modeling of CNT Field-Emission Devices

Koohsorkhi J., Rouhi N., Abdi Y., Mohajerzadeh S., Robertson M.D., Thompson R.D., Acadia University, CA

We report the fabrication of field-emission devices based on vertically aligned carbon nanotubes that possess a novel gate structure with applications in flat-panel displays, nanolithography systems and new sensor technologies. The devices consist of CNTs [...]

Development of Carbon Nanotubes Vacuum Field Emission Devices

Kang W.P., Wong Y.M., Davidson J.L., Kerns D.V., Huang J.H., Galloway K.F., Vanderbilt University, US

This report focuses on the design, fabrication and characterization of vacuum field emission (VFE) devices, specifically on the triode and integrated differential amplifier (diff-amp), utilizing CNTs synthesized by microwave plasma chemical vapor deposition in conjunction [...]

Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors

Paim V.C., Galup-Montoro C., Schneider M.C., Federal University of Santa Catarina, BR

In this communication we present a charge-based formulation for the thermal noise in short-channel MOS transistors. We arrive at a closed expression for the channel noise including velocity saturation for all the operating regions of [...]

A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram

Wu H.C., Mijalkovic S., Burghartz J.N., Delft University of Technology, NL

A unified parameters extraction procedure for temperature and geometry scalable bipolar transistor model Mextram has been demonstrated using an example of high-speed SiGe HBT technology. The essential feature of the proposed methodology is a direct [...]

Interrelations between Threshold Voltage Definitions and Extraction Methods

Schneider M.C., Galup-Montoro C., Machado M.B., Cunha A.I.A., Federal University of Santa Catarina, BR

This paper presents a brief discussion on the main MOSFET threshold voltage definitions available in the literature as well as on associated extraction methodologies. In order to compare these definitions and methodologies, we take advantage [...]

Static Analog Design Methodology

Guigues F., Rudolff F., Kussener E., L2MP UMR 6137 CNRS - ISEN-Toulon, FR

When strong constraints of supply voltage (< 1V ) and bias current (< 100nA) are required, the only way to meet design’sspecifications without using huge silicon area consists on decreasing transistor’s inversion level and therefore [...]

A transient circuit model for a phase change memory element

Huizing H.G.A., Tio Castro D., Paasschens J.C.J., Lankhorst M.H.R., Philips, NL

A transient lumped element model for a phase change memory (PCM) cell is developed for use in a circuit simulator. Unlike existing models, this model calculates threshold voltage and off-state resistance drift as found in [...]

Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology

Williams R.Q., Chidambarrao D., McCullen J.H., Narasimha S., Mitchell T.G., Onsongo D., IBM Corporation, US

This work presents a novel methodology for a physically-based, layout-dependent nitride liner stress model that works with readily-available compact models. The methodology includes a data-calibrated, semi-empricial model and is tightly-coupled to circuit netlist extraction for [...]

Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs

Nawal S., Venkataraman V., Kumar M.J., Indian Institute of Technology, IN

A simplae compact model for the threshold voltage of Strained Si/SiGe MOSFET is reported for the first time. This model accurately predicts the effects of Ge content and other device parameters on threshold voltage. The [...]

A Circuit-Compatible Model for Ballistic Silicon Nanowire Transistors

Chen J., Agere Systems, US

Silicon nanowire transistors (SNWT) are being extensively explored as a successor to CMOS. Silicon nanowires with a diameter as small as 2nm and having high carrier mobility have been achieved. Such developments shed light on [...]