Compact Modeling

High Conentration of Interface Traps in MOS Transistor Modeling

Chen Z., Jie B.B., Sah C-T, Xiamen University, CN

Modifications of the MOS capacitor and transistor characteristics by the presence of a high concentration of interface traps are described. Change or distortion of the gate/base voltage dependent characteristics are presented, such as the gate [...]

A History of Electronic Traps on Silicon Surfaces and Interfaces

Sah C-T, Jie B.B., Chen Z., University of Florida, US

A review of the electronic or electron and hole traps on silicon surfaces and interfaces is given. They are increasingly affecting the electrical signal properties of silicon diodes and transistors as the technologies for digital, [...]

HiSIM2.4.0: Advanced MOSFET model for the 45nm Technology Node and Beyond

Miura-Mattausch M., Sadachika N., Miyake M., Navarro D., Ezaki T., Mattausch H.J., Miura-Mattausch M., Ohguro T., Iizuka T., Taguchi M., Miyamoto S., Inagaki R., Furui Y., Hiroshima University, JP

HiSIM realizes both accurate and fast circuit simulation. The newly developed HiSIM2.4.0 includes required features in modeling for the 45nm technology node and beyond such as the STI stress effect. A major development is an [...]

Consistency of compact MOSFET models with the Pao-Sah formulation: consequences for small-signal analysis

Galup-Montoro C., Schneider M.C., Cunha A.I.A., Federal University of Santa Catarina, BR

Compact models for the MOSFET are based on the decomposition of the two-dimensional problem into two one-dimensional problems. Since a compact MOSFET model core consists of an input voltage equation, and an output current equation, [...]

Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors

Paim V.C., Galup-Montoro C., Schneider M.C., Federal University of Santa Catarina, BR

In this communication we present a charge-based formulation for the thermal noise in short-channel MOS transistors. We arrive at a closed expression for the channel noise including velocity saturation for all the operating regions of [...]

A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram

Wu H.C., Mijalkovic S., Burghartz J.N., Delft University of Technology, NL

A unified parameters extraction procedure for temperature and geometry scalable bipolar transistor model Mextram has been demonstrated using an example of high-speed SiGe HBT technology. The essential feature of the proposed methodology is a direct [...]

Topic: Compact Modeling

High Conentration of Interface Traps in MOS Transistor Modeling

A History of Electronic Traps on Silicon Surfaces and Interfaces

HiSIM2.4.0: Advanced MOSFET model for the 45nm Technology Node and Beyond

Consistency of compact MOSFET models with the Pao-Sah formulation: consequences for small-signal analysis