High Conentration of Interface Traps in MOS Transistor Modeling

, ,

Keywords: , , , ,

Modifications of the MOS capacitor and transistor characteristics by the presence of a high concentration of interface traps are described. Change or distortion of the gate/base voltage dependent characteristics are presented, such as the gate capacitance at high- and low-frequencies (with respect to the trapping frequencies), base recombiantion conductance and current (R-DCIV), drain and source currents. Parameters cover the basewell (body) impurity concentration of 1E16 to 1E19 cm-3 and interface trap concentration of 1E08 to 1E14 cm-2, corresponding to unstressed logic-RF and end-of-life memory transistors. A statistical-physics-based mathematical model equation is employed to cover all types of one-trapped-electron (or hole) interface traps including the short-range neutral and the long-range Coulombic trapping potential wells, respectively from spatially distributed random bond angles and lengths, and from isolated impurity ions.

PDF of paper:

Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: May 20, 2007
Pages: 493 - 498
Industry sector: Sensors, MEMS, Electronics
Topic: Compact Modeling
ISBN: 1-4200-6184-4