Papers – Page 691 – TechConnect Briefs

Simulating CMOS Circuits Containing Multiple FET Types Including the Geometric Dependence of Correlation between FET Types

Park J-E, Park S-J, Liang C-H, Assenmacher J., Watts J., Park J-E, Park S-J, Wachnik R., IBM, US

MOSFET device of similar design but different threshold voltage are often built on a single chip. It is important to be able to simulate with a compact model the variation of such devices including the [...]

Modeling Process Variations Using a Compact Model

Murali R., Meindl J.D., Georgia Tech, US

Inclusion of manufacturing variations has become an important part of static timing analysis. Existing statistical timing analysis methods involve the use of time-consuming circuit simulations or use fit polynomials. Previous efforts at modeling parameter variations [...]

Modeling MOSFET Process Variation using PSP

Watts J.S., Lee Y.M., Park J-E, IBM, US

The PSP model has been extensively evaluated for it’s abililty accurately match IV and CV characteristics MOSFETs measured on a single die. This enables accurate prediction of circuit behavior for circuits made of transistors which [...]

Modeling of FET Flicker Noise and Impact of Technology Scaling

Chen C-Y, Liu Y., Cao S., Dutton R., Sato-Iwanaga J., Inoue A., Sorada H., Stanford University, US

Ongoing scaling of device dimensions, including the introduction of new channel materials and device structures, as well as the incorporation of novel gate-stack materials, has major implications on noise performance metrics. In particular, flicker noise [...]

Carbon Nanotube Transistor Compact Model

Deng J., Wan G.C., Wong H.-S., Stanford University, US

The principal challenges for the semiconductor industry at the nanoscale are: (1) power and performance optimization, (2) device fabrication and control of variations at the nanoscale, and (3) integration of a diverse set of materials [...]

Unified Compact Model for Generic Double-Gate MOSFETs

Zhou X., See G.H., Zhu G.J., Zhu Z.M., Chandrasekaran K., Zhu G.J., Zhu Z.M., Rustagi S.C., Lin S-H, Wei C.Q., Lim G.H., Nanyang Technological University, SG

A generic double-gate (DG) MOSFET follows a generalized (input) voltage equation from the first integral of Poisson equation and Gauss' law at the two gates, which is implicit and, in general, non-integrable when the channel [...]

Analytic Charge Model for Double-Gate and Surrounding-Gate MOSFETs

Yu B., Lu H., Lu W-Y, Lu H., Lu W-Y, Taur Y., UCSD, US

An analytic charge model for both double-gate (DG) and surrounding-gate (SG) MOSFETs is presented. With only the mobile charge term, Poisson’s equation is rigorous solved and the analytic electrostatic potential is derived. The development of [...]

A Unified View of Drain Current Models for Undoped Double-Gate SOI MOSFETs

Ortiz-Conde A., García-Sánchez F.J., Simón Bolívar University, VE

In this paper we discuss the compact modeling framework for undoped double-gate SOI MOSFETs. Core compact models, including the analysis for surface potential and drain current for various device structures are discussed and compared. Then, [...]

A PSP based scalable compact FinFET model

Smit G.D.J., Scholten A.J., Serra N., Pijper R.M.T., van Langevelde R., Mercha A., Gildenblat G., Klaassen D.B.M., NXP Semiconductors, NL

A high-quality compact FinFET model is a prerequisite for initial circuit design and evaluation of these prospective replacements for conventional bulk MOSFETs. Our PSP-based compact model for symmetric 3-terminal FinFETs with thin undoped or lightly [...]

3-D Analytical Models for the Short-Channel Effect Parameters in Undoped FinFET Devices

Hamid H.A., Roig J., Universitat Rovira i Virgili, ES

We present 3-D analytical models for subthreshold swing, threshold voltage and threshold volatge roll-off of undoped FinFET devices. After solving the 3-D Poisson equation, in which the mobile charge term was included, we have obtained [...]