FinFET – TechConnect Briefs

Hot Carrier Effect and Oxide Reliability of T-FinFET Devices

He J., He X., He Y., Hu G., Li C., Liu J., He J., He X., He Y., Liu J., Ma G., He J., He X., He Y., Pan J., SoC Key Laboratory, Peking University Shenzhen Institute and PKU-HKUST Shenzhen-Hong Kong Institution, CN

Hot-carrier effect and oxide reliability of CMOS T-FinFET with 2.1nm-thick gate-SiO2 were investigated. It was found that hot-carrier immunity improves as the T-FinFET fin width (body thickness) decreases, which facilitates gate-length scaling, while it is [...]

New Elements and Features in the Process Design Kits for a FinFET Technology

Lu N., Baizley A., Guan X., Johnson J., McCullen J., Ozbek A., Rahman A., Wang H., Yu M., Zemke C., Rausch W., Wachnik R., IBM, US

Parasitic resistance is a primary performance constraint in FinFET technologies. We report that new and innovative elements and features have been introduced into Process Design Kits for 14nm FinFET technology. They enable accurate and efficient [...]

3-D Thermal Simulator Dedicated for Modern Silicon Structures

Zubert M., Raszkowski T., Janicki M., Samson A., Jankowski M., Napieralski A., Lodz University of Technology, PL

The accurate thermal modelling of nanoscale chips is of vital importance, as heat dissipation is arguably one of the most important problems in modern integrated circuits. As the technology node is expected to continue to [...]

A New Method to Fin-width Line Edge Roughness Effect Simulation of FinFET Performance

Zhu Y., Zhao W., Wang W., Wu W., Feng Z., He J., He P., He J., He P., Song L., Peking University Shenzhen SOC Key Laboratory, CN

This paper developed a full three-dimensional (3-D) statistical simulation method to investigate Fin-width Line Edge Roughness (LER) effect on the FinFETs performance. The line edge roughness is introduced by Matlab program, and then the intrinsic [...]

The Heat transfer in Fin-FET transistor

Zubert M., Janicki M., Raszkowski T., Samson A., Napieralski A., Lodz University of Technology, PL

The electro-thermal analysis is one of the most important development steps in the professional design of analogue submicron electric ICs, power modules design process as well as modern nanostructures. This analysis is useful to power [...]

Heterogeneous Nano-electronic Devices Enabled by Monolithic Integration of IIIV, Ge, and Si to expand future CMOS functionality

Thean A.V-Y., Collaert N., Waldron N., Merckling C., Witters L., Loo R., Mitard J., Rooyackers R., Vandooren A., Verhulst A., Veloso A., Pourghaderi A., Eneman G., Yakimets D., Huynh Bao T., Garcia Bardon M., Ryckaert J., Dehan M., Wambacq P., Caymax M., IMEC, BE

3D-IC’s by stacking and connecting dies of different functions with through-silicon via processes are emerging as an upcoming heterogeneous SOC enabler. Since connectivity between stacked layers may be limited by nearest-neighbor layers, the stagnation of [...]

Compact Negative Bias Temperature Instability Model for Nanoscale FinFET Reliability Simulation

Zhang C., Wang W., Liu Y., Ye Y., Zhao W., He J., Wu W., Peking University Shenzhen SOC Key Laboratory, CN

A compact Negative Bias Temperature Instability (NBTI) model, which is based on a novel Reaction-Trapping (R-T) theory, is proposed to predict the static and dynamic NBTI degradation in nanoscale FinFET reliability simulation. This R-T theory [...]

InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG

Khandelwal S., Duarte J.P., Paydavosi N., Chauhan Y.S., Gu J.J., Si M., Ye P.D., Hu C., University of California-Berkeley, US

In this paper, we present modeling results for InGaAs FinFETs using the industry standard compact model BSIM-CMG. We show that BSIM-CMG produces excellent fits to the measured I-V data of these devices. The difference seen [...]

SOI-Multi-FinFET: Impact of Fins Number multiplicity on Corner Effect

Moulai Khatir A.N., Guen-Bouazza A., Bouazza B., Guen-Bouazza A., UABT, DZ

SOI-Multifin-FET shows excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency. In this work, we analyzed this combination by a three-dimensional numerical device simulator [...]

Performance Comparison of Non-planar MOSFETs

Liao Y.-B., Chiang M-H, Hsu W.-C., National Ilan University, TW

To gain insights into device variability, device scalability and even circuit performance, more comprehensive simulation data are presented. FinFET shows the highest transconductances corresponding to aforementioned highest IDLIN and IDSAT. Regarding process variation, same W¬Si/D [...]