Compact Modeling – Page 19 – TechConnect Briefs

Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs

Kranti A., Armstrong G.A., Queen’s University of Belfast, UK

In the present paper, a compact model for short channel effects (SCEs) in source/drain engineered nanoscale DG MOSFET, is proposed for the first time and the impact of spacer width (s), lateral source/drain doping gradient [...]

Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability

Goel K., Saxena M., Gupta M., Gupta R.S., Gupta M., Gupta R.S., Professor, IN

We have modeled a new structure TRIMGAS which has 3 gate materials in the gate and an oxide stack. we have compared various parameters to see whether this strucure is superior to any of our [...]

Compact modeling and performance analysis of Double-Gate MOSFET-based circuits

Tintori O., Munteanu D., Loussier X., Autran J-L, Regnier A., Bouchakour R., L2MP, FR

Double-Gate (DG) MOS transistors and related multiple-gate device architectures are nowadays widely identified as one of the most promising solutions for meeting the roadmap requirements for the end-of-the-roadmap integration. One of the identified challenges for [...]

Compact Model of drain-current in Double-Gate MOSFETs including carrier quantization and short-channel effects

Loussier X., Munteanu D., Autran J-L, Harrison S., Cerutti R., L2MP, FR

Double-Gate (DG) structure has been in the last years the object of intensive research because its enormous potentiality to push back the integration limits to which conventional devices are subjected. Although the operation of DG [...]

A Computationally Efficient Method for Analytical Calculation of Potentials in Undoped Symmetric DG SOI MOSFET

Cobianu O., Glesner M., Darmstadt University of Technology, DE

In order to build an analytical model of an undoped symmetric DG SOI MOSFET devices, an accurate but rather difficult method was used by S. Malobabic et.al. [2] in their papers that is based on [...]

Capacitance Model for Four-Terminal DG MOSFETs

Nakagawa T., Sekigawa T., Tsutsumi T., Hioki M., O’uchi S., Koike H., National Institute of Advanced Industrial Science and Technology, JP

We present an intrinsic-capacitance model for undoped-channel full-deplete DG MOSFETs with two independent gates of different gate-oxide thickness. It includes carrier-velocity saturation, and mobility change by the surface electric-field. We considered five intrinsic capacitances Cg1s, [...]

Topic: Compact Modeling

Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs

Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability

Compact modeling and performance analysis of Double-Gate MOSFET-based circuits

Compact Model of drain-current in Double-Gate MOSFETs including carrier quantization and short-channel effects

A Computationally Efficient Method for Analytical Calculation of Potentials in Undoped Symmetric DG SOI MOSFET

Capacitance Model for Four-Terminal DG MOSFETs

Explicit Threshold Voltage Based Compact Model of Independent Double Gate MOSFET

Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach

A Carrier Based Analytic Model for Undoped Surrounding-Gate MOSFETs

Compact Capacitance Model of LDMOS for Circuit Simulation