Compact Modeling – Page 18 – TechConnect Briefs

Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology

Williams R.Q., Chidambarrao D., McCullen J.H., Narasimha S., Mitchell T.G., Onsongo D., IBM Corporation, US

This work presents a novel methodology for a physically-based, layout-dependent nitride liner stress model that works with readily-available compact models. The methodology includes a data-calibrated, semi-empricial model and is tightly-coupled to circuit netlist extraction for [...]

Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs

Nawal S., Venkataraman V., Kumar M.J., Indian Institute of Technology, IN

A simplae compact model for the threshold voltage of Strained Si/SiGe MOSFET is reported for the first time. This model accurately predicts the effects of Ge content and other device parameters on threshold voltage. The [...]

A Circuit-Compatible Model for Ballistic Silicon Nanowire Transistors

Chen J., Agere Systems, US

Silicon nanowire transistors (SNWT) are being extensively explored as a successor to CMOS. Silicon nanowires with a diameter as small as 2nm and having high carrier mobility have been achieved. Such developments shed light on [...]

A Compact Model of Ballistic CNFET for Circuit Simulation

Paul B.C., Fujita S., Okajima M., Lee T., Toshiba America Research Inc., US

As silicon technology is approaching to its limit, Carbon nanotube FETs (CNFET) are shown to have potential of taking this place in the post silicon era. Consequently, interests have grown to predict the performance of [...]

Enhanced Junction Capacitance Modeling

Anderson F.G., Rassel R.M., Lavoie M.A., IBM Microelectronics, US

The current standard diode junction capacitance models do not yield high quality models for hyperabrupt junction varactors that are constructed from several implants. We describe a new enhancement that employs the actual (exponential) doping profiles [...]

A Simple Yet Accurate Mismatch Model For Circuit Simulation

Jin Z., Lee Y.M., Watts J.S., Bonaccio A.R., Schroer G.J., Pai N.G., IBM, US

As technology scales, mismatch between a pair of transistors becomes a more and more critical issue for technology development and circuit designs. Scaling also increases the complexity of compact device modeling. Sophisticated models are usually [...]

Dynamic Behavior Model for High-k MOSFETs

Dunga M.V., Xi X., Niknejad A.M., Hu C., University of California-Berkeley, US

High-K dielectrics need to be introduced into bulk CMOS to extend the scaling limits. However, the use of high-k dielectrics introduces new dynamic behavior into transistor operation. Pulsed measurements show hysteresis in drain current (Id), [...]

On Idlow with Emphasis on Speculative SPICE Modeling

Chen Q., Wu Z-Y, Icel A.B., Goo J-S, Krishnan S., Thuruthiyil C., Subba N., Suryagandh S., An J.X., Ly T., Radwin M., Yonemura J., Assad F., Advanced Micro Devices, US

An empirical correlation model of Idlow, the MOSFET drain current measured at Vgs=Vdd/2 and Vds=Vdd, where Vdd is the supply voltage, is proposed based on the alpha-power law model. It enables a comprehensive analysis of [...]

SOI CMOS Compact Modeling based on TCAD Device Simulations

Botula A., Furkay S., Sheridan D.C., Johnson J.M., Na M-H, IBM Corporation, US

This work describes a TCAD-based methodology for generating compact models for circuit design in advance of hardware availability (predictive modeling). The exercise was performed on a 65nm node SOI CMOS technology. TCAD simulations accurate enough [...]

Compact Models for Double Gate and Surrounding Gate MOSFETs

Abebe H., Cumberbatch E., Morris H., Uno S., San Jose State University, US

The models presented by Lu and Taur, [1], for lightly doped double gate and surrounding gate MOSFETs each require numerical solution of a transcendental equation. In this paper we present explicit, analytic solutions of these [...]