Zhang A. – TechConnect Briefs

Improved Electric Field Decomposition Capacitance Model with 3-D Terminal and Fringe Components in Sub-28nm Interconnect

Zhang A., Li C., Liu J., He J., He X., He Y., Liu J., He J., He X., He Y., Ma G., Pan J., He J., He X., He Y., Hu G., Peking University Shenzhen Institute and PKU-HKUST Shenzhen-Hong Kong Institution, CN

In this paper, a parasitic capacitance model for a finite single three-dimensional (3-D) wire above an infinite plate in the nano-scale 3-D integrated circuit application is developed based on electric field decomposition (EFD). The capacitance [...]

Junctionless Nanowire MOSFET with Dynamic Threshold Voltage Operation Methodology

Mei J., Zhang A., Yu C., Ye Y., Wang H., Deng W., He J., PKU-HKUST Shenzhen-Hongkong Institution, CN

In this paper, a junctionless nanowire MOSFET with the dynamic threshold voltage operation methodology （DT-JNT） is proposed and its characteristics are studied comparing with those of a conventional junctionless nanowire transistor (JNT) and a double-gate [...]

Numerical Study on Gate-All-Around Tunneling FET with SiO2 Core and Si Shell Structure

Zhang A., Zhang L., Zhang X., Zhang A., Zhang L., Zhang X., Mei J., Zhang A., Zhang L., Zhang X., He H., He J., He H., He J., Chan M., PKU-HKUST Shenzhen-Hongkong Institution, CN

This work presents a gate-all-around tunneling FET based on SiO2 core and Si shell structure (GAA-SOI-TFET) and demonstrates its performance characteristics via the numerical simulation method. The 3-D T-CAD numerical simulations demonstrate that this new [...]

Active Pixel CMOS Image Sensor with Single Transistor Architecture

Liang H., Zhang A., Zhang D., Zhang G., Zhang A., Zhang D., Zhang G., He J., Su Y., Zhang A., Zhang D., Zhang G., PKU-HKUST Shenzhen-Hongkong Institution, CN

CMOS active pixel image sensor with single transistor architecture (1T CMOS APS) is proposed in this paper and verified by experiment data. By switching the photo sensing pinned diode, reset and select can be achieved [...]

Field-Based 3D Capacitance Modeling for sub-45-nm On-Chip Interconnect

Zhang A., Zhao W., Ye Y., He J., Chen A., Chan M., Beijing University of Aeronautics and Astronautics, CN

Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes the electric field into various regions and gives solutions for each part. The total ground capacitance is the summation of all components. [...]

Modeling of Dynamic Threshold Voltage of High K Gate Stack and Application in FinFET Reliability

He H., He J., Ma C., Wang C., Zhang A., He H., He J., Peking Univeristy, CN

A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model [...]