In this paper, a parasitic capacitance model for a finite single three-dimensional (3-D) wire above an infinite plate in the nano-scale 3-D integrated circuit application is developed based on electric field decomposition (EFD). The capacitance components at wire ends, i.e., the 3-D terminal and terminal fringe capacitance, are considered by the 3-D electric field analysis. Verified by extensive COMSOL simulations, the model can accurately predict parasitic capacitance for a wide range of 3-D BEOL wire dimensions in the beyond 28nm CMOS process technology.
Journal: TechConnect Briefs
Volume: TechConnect Briefs 2019
Published: June 17, 2019
Pages: 279 - 282
Industry sector: Sensors, MEMS, Electronics
Topicss: Nanoelectronics, Sensors - Chemical, Physical & Bio