US – Page 299 – TechConnect Briefs

Simulating CMOS Circuits Containing Multiple FET Types Including the Geometric Dependence of Correlation between FET Types

Park J-E, Park S-J, Liang C-H, Assenmacher J., Watts J., Park J-E, Park S-J, Wachnik R., IBM, US

MOSFET device of similar design but different threshold voltage are often built on a single chip. It is important to be able to simulate with a compact model the variation of such devices including the [...]

Modeling Process Variations Using a Compact Model

Murali R., Meindl J.D., Georgia Tech, US

Inclusion of manufacturing variations has become an important part of static timing analysis. Existing statistical timing analysis methods involve the use of time-consuming circuit simulations or use fit polynomials. Previous efforts at modeling parameter variations [...]

Modeling MOSFET Process Variation using PSP

Watts J.S., Lee Y.M., Park J-E, IBM, US

The PSP model has been extensively evaluated for it’s abililty accurately match IV and CV characteristics MOSFETs measured on a single die. This enables accurate prediction of circuit behavior for circuits made of transistors which [...]

Modeling of FET Flicker Noise and Impact of Technology Scaling

Chen C-Y, Liu Y., Cao S., Dutton R., Sato-Iwanaga J., Inoue A., Sorada H., Stanford University, US

Ongoing scaling of device dimensions, including the introduction of new channel materials and device structures, as well as the incorporation of novel gate-stack materials, has major implications on noise performance metrics. In particular, flicker noise [...]

Carbon Nanotube Transistor Compact Model

Deng J., Wan G.C., Wong H.-S., Stanford University, US

The principal challenges for the semiconductor industry at the nanoscale are: (1) power and performance optimization, (2) device fabrication and control of variations at the nanoscale, and (3) integration of a diverse set of materials [...]

Analytic Charge Model for Double-Gate and Surrounding-Gate MOSFETs

Yu B., Lu H., Lu W-Y, Lu H., Lu W-Y, Taur Y., UCSD, US

An analytic charge model for both double-gate (DG) and surrounding-gate (SG) MOSFETs is presented. With only the mobile charge term, Poisson’s equation is rigorous solved and the analytic electrostatic potential is derived. The development of [...]

A Versatile Multigate MOSFET Compact Model: BSIM-MG

Hu C., Dunga M., Lin C.H., Lu D., Niknejad A., University of California-Berkeley, US

BSIM-MG is a surface-potential based compact model for multi-gate MOSFETs such as FinFETs fabricated on either SOI or bulk substrates. It can model transistors with the gate controlling two, three, or four sides of the [...]

Modeling of Saturation-Region Characteristics of Nanoscale Double-Gate MOSFETs

Fossum J.G., Chouksey S., University of Florida, US

Saturation-region effects, unique to double-gate (DG) MOSFETs, are discussed and modeled in UFDG. The effects include carrier velocity overshoot and drain-induced charge enhancement (DICE). The former, modeled in terms of carrier temperature, implies ballistic-like currents [...]

A History of Electronic Traps on Silicon Surfaces and Interfaces

Sah C-T, Jie B.B., Chen Z., University of Florida, US

A review of the electronic or electron and hole traps on silicon surfaces and interfaces is given. They are increasingly affecting the electrical signal properties of silicon diodes and transistors as the technologies for digital, [...]

Monolithic Concept and the Inventions of Integrated Circuits by Kilby and Noyce

Saxena A.N., Rensselaer International Science Company, US

Getting history right is an important matter. It is in that spirit that this paper has been written about the invention of integrated circuits (ICs). The invention of ICs has been one of the most [...]