Compact Modeling – Page 7 – TechConnect Briefs

A Continuous Compact Model of Short-Channel Effects for Undoped Cylindrical Gate-All-Around MOSFETs

Cousin B., Reyboz M., Rozeau O., Jaud M-A, Ernst T., Jomaah J., CEA/LETI/MINATEC, FR

A continuous and explicit compact model of short-channel effects (SCEs) for undoped cylindrical Gate-All-Around (GAA) MOSFETs is presented in this paper. SCEs are implemented into an analytic and continuous drain-current model based on a surface [...]

Analytical Modeling of the Subthreshold Electrostatics of Nanoscale GAA Square Gate MOSFETs

Vishvakarma S.K., Fjeldly T.A., Norwegian University of Science and Technology, NO

An analytical model is presented for the 3-D electrostatics of lightly doped GAA square gate MOSFETs operating in the subthreshold domain. The model is based on the assumption of parabolic potential distributions in the directions [...]

Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model

Zhou X., Zhu G.J., Srikanth M.K., Lin S-H, Chen Z.H., Zhang J.B., Wei C.Q., Yan Y.F., Selvakumar R., Nanyang Technological University, SG

This paper presents benchmark tests of the unified compact model (Xsim) for double-gate (DG) and gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs, which has been developed over the years with the unified regional modeling (URM) approach. The [...]

Source/Drain Edge Modeling for DG MOSFET Compact Model

Nakagawa T., O’uchi S., Sekigawa T., Tsutsumi T., Hioki M., Koike H., AIST (National Institute of Advanced Industrial Science and Technology), JP

A compact model for four terminal double-gate MOSFET, based on double charge-sheet approximation with carrier velocity saturation, is discussed. Although it is a monolithic model both for conductance and intrinsic capacitances, it is not a [...]

Analytic Channel Potential Solution of Symmetric DG AMOSFETs

Chen L., Xu Y., Zhang L., Zhou W., Zhou X., Zhou W., Zhou X., He J., Peking University, CN

This paper presents an analytic channel potential solution of the symmetrical DG AMOSFETs. The proposed solution is derived from complete 1-D Poisson-Boltzmann equation by taking three components of net charge density (fixed charge, holes and [...]

Electrostatic Potential Compact Model for Symmetric and Asymmetric Lightly Doped DG-MOSFET Devices

Abebe H., Cumberbatch E., Uno S., Tyree V., USC/ISI, US

The analytical symmetric and asymmetric lightly doped DG-MOSFET device electrostatic potential compact model presented here improves the compact model accuracy without any iteration. The model is developed using the Lambert Function and a 2-dimensional (2-D) [...]

Subthreshold Quantum Ballistic Current and Quantum Threshold Voltage Modeling for Nanoscale FinFET

Monga U., Fjeldly T.A., UniK/Norwegian University of Science and Technology, NO

A subthreshold quantum ballistic current model and a quantum threshold voltage model is presented for nanoscale FinFET.The eigenvalues are determined by solving Schrödinger equation along the gate-to-gate axis. The current is then modeled using Natori’s [...]

A Unified Charge-Based Model for SOI MOSFETs Valid from Intrinsic to Heavily Doped Channel

Zhang J., Zhang L., He J., Zhang J., Zhang L., Zhou X., Zhou Z., Zhou X., Zhou Z., Peking University, CN

A unified charge-based model for SOI MOSFETs is presented. The proposed model is valid and accurate from intrinsic to heavily doped channel with various structure parameter variations. The framework starts from one-dimension Poisson-Boltzmann’s equation. Based [...]

Modeling of Gate Leakage, Floating Body Effect, and History Effect in 32nm HKMG PD-SOI CMOS

Deng Y., Rupani R.A., Johnson J., Springer S., IBM, US

The gate leakage, floating body effect, and history effect in 32nm HKMG PD-SOI CMOS have been extensively studied and analyzed. Based on the measured data, a comprehensive HKMG PD-SOI gate leakage model has been developed [...]

Impact of Gate-Induced-Drain-Leakage current modeling on circuit simulations in 45nm SOI technology and beyond

Wang H., Williams R., Wagner L., Johnson J., Hyde P., Springer S., IBM, US

Gate Induced Drain Leakage (GIDL) current is one of the most important leakage components in Silicon-on-Insulator (SOI) MOSFET devices. The effect of GIDL current reported before mainly focused on device characteristics in the OFF-state or [...]