compact modeling – Page 4 – TechConnect Briefs

A Carrier Based Analytic Model for Undoped Surrounding-Gate MOSFETs

He J., Zhang X., Chan M., Wang Y., Peking University, CN

A carrier-based analytic DCIV model for the undoped cylindrical surrounding-gate MOSFETs is presented in this paper. It is based on an exact solution of the Poisson equation and a Pao-Sah current formulation in terms of [...]

Charge-storage calculation for Si-based bipolar transistors from device simulation

Tran H., UCSD, US

Various methods for calculating regional charge storage components in bipolar transistors fromdevice simulation results are compared with respect to their usefulness for compact modeling. Themethods are evaluated for Si and SiGe transistors with very different [...]

Analog Compact Modeling for a 20-120V HV CMOS Technology

Seebacher E., Posch W., Molnar K., Huszka Z., austriamicrosystems AG, AT

In this paper we discuss state of the art and new developments of analog modeling for HV CMOS technologies. We will give a detailed overview about the full characterization of a 0.35um high voltage process [...]

High-Voltage LDMOS Compact Modeling

Willemsen M.B., van Langevelde R., Klaassen D.B.M., Philips Research, NL

In compact modeling of high-voltage LDMOS devices often a sub-circuit approach is used. While for the channel region a standard compact MOS model (for example BSIM4, MM11 or PSP) is used, the drift region is [...]

An Explicit Quasi-Static Charge-Based Compact Model for Symmetric DG MOSFET

Prégaldiny F., Krummenacher F., Sallese J.M., Diagne B., Lallement C., InESS, FR

This paper presents a closed-form compact model for the undoped double-gate (DG) MOSFET under symmetrical operation. This charge-based model aims at giving a comprehensive understanding of the device from the circuit design point of view. [...]

BSIM4 and BSIM Multi-Gate Progress

Dunga M.V., Lin C.H., Xi X., Chen S., Lu D.D., Niknejad A.M., Hu C., UC-Berkeley, US

Compact models form an integral part of any circuit design environment, ranging from analog and digital design to mixed-signal design worlds. The models need to be developed and improved in parallel with technology advancements to [...]

Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling

Zhou X., Chandrasekaran K., Chiah S.B., Shangguan W., Zhu Z., See G.H., Mani Pandey S., Lim G.H., Rustagi S., Cheng M., Chu S., Hsia L.-C., Nanyang Technological University, SG

In this paper, we extend our unified regional approach to bulk-MOS charge modeling with non-pinned surface potential for various device structures such as PD/FD/UTB SOI and s-DG MOSFETs, including strained-Si channel. The regional solutions make [...]

Halo Doping: Physical Effects and Compact Modeling

Mudanai S., Rios R., Shih W-K, Packan P., Lee S-W., Intel Corp., US

As the devices are scaled to ultra short channel lengths, pocket or halo implants have been used widely to reduce DIBL and other short channel effects. Although, the use of halo implants helps with control [...]

Benchmark Tests on Conventional Surface Potential Based Charge-Sheet Models And the Advanced PUNSIM Development

He J., Song Y., Niu X., Zhang G., Zhang X., Zhang G., Zhang X., Huang R., Chan M., Wang Y., Peking University, CN

This paper reports the benchmark test results of surface potential solution, inversion charge and channel current calculation, and short-channel effect model of various surface based charge-sheet models and our PUNSIM development to breakthrough the drawbacks [...]

Compact Modeling for RF and Microwave Integrated Circuits

Niknejad A.M., Chan M., Hu C., Brodersen B., Xi J., He J., Emami S., Doan C., Cao Y., Su P., Wan H., Dunga M., Lin C.H., University of California at Berkeley, US

Compact modeling has been an integral part of the design of integrated circuits for digital and analog applications. The availability of scalable CMOS device models has enabled rapid simulation and design of present and future [...]