compact model – Page 3 – TechConnect Briefs

Compact Models for sub-22nm MOSFETs

Chauhan Y.S., Lu D., Venugopalan S., Morshed T., Karim M.A., Niknejad A., Hu C., University of California-Berkeley, US

FinFET and UTBSOI FET (or ETSOI) are the two promising multi-gate FET candidates for sub-22nm CMOS technology. BSIM multi-gate FET models (BSIM-CMG and BSIM-IMG) are the surface potential based physical compact models for FinFET and [...]

Guidelines for Verilog-A Compact Model Coding

Depeyrot G., Poullet F., Dolphin Integration, FR

Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for both simulation and synthesis (IEEE1364-2001 and [...]

Compact Modeling of Signal Transients for Dispersionless Interconnects With Resistive, Capacitive and Inductive Terminal Loads

Liu Chi, Zhou Z., Lin X., Xia J., Zhang X., He J., Peking University, CN

In this paper, compact models for transient response of dispersionless interconnects are rigorously derived with resistive, inductive and capacitive terminal loads. The proposed compact models are verified by the HSPICE simulation with high accuracy and [...]

Analytical model of quantum threshold voltage in short-channel nanowire MOSFET including band structure effects

Dura J., Martinie S., Munteanu D., Jaud M-A, Barraud S., Autran J-L, CEA/LETI/MINATEC, FR

The particular shape of Gate-All-Around (GAA) nanowires allows a much higher electrostatic control of the active region than conventional devices, as required for the integration at the end-of-roadmap. This architecture is suitable for ultra-scaled devices [...]

Analytical Solution of Surface Potential for Un-Doped Surrounding-Gate MOSFET

Dey A., DasGupta A., Arizona State University, US

Surrounding-Gate MOS transistors are seen as viable slternative to the problems of bulk MOSFET in deep sub-micron region. However modeling of drain current and capacitances, like other MOS structures require solution of an implicit equation. [...]

Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model

Zhou X., Zhu G.J., Srikanth M.K., Lin S-H, Chen Z.H., Zhang J.B., Wei C.Q., Yan Y.F., Selvakumar R., Nanyang Technological University, SG

This paper presents benchmark tests of the unified compact model (Xsim) for double-gate (DG) and gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs, which has been developed over the years with the unified regional modeling (URM) approach. The [...]

Source/Drain Edge Modeling for DG MOSFET Compact Model

Nakagawa T., O’uchi S., Sekigawa T., Tsutsumi T., Hioki M., Koike H., AIST (National Institute of Advanced Industrial Science and Technology), JP

A compact model for four terminal double-gate MOSFET, based on double charge-sheet approximation with carrier velocity saturation, is discussed. Although it is a monolithic model both for conductance and intrinsic capacitances, it is not a [...]

A Unified Charge-Based Model for SOI MOSFETs Valid from Intrinsic to Heavily Doped Channel

Zhang J., Zhang L., He J., Zhang J., Zhang L., Zhou X., Zhou Z., Zhou X., Zhou Z., Peking University, CN

A unified charge-based model for SOI MOSFETs is presented. The proposed model is valid and accurate from intrinsic to heavily doped channel with various structure parameter variations. The framework starts from one-dimension Poisson-Boltzmann’s equation. Based [...]

Dynamic Compact Thermal Model of an Electrothermal Micromirror Based on Transmission Line Theory

Pal S., Xie H., University of Florida, US

The two main challenges in electrothermal MEMS design are their slow response and inherently low efficiency. Therefore, thermal modeling is essential for design and optimization. A compact parametric model is desirable as it computationally efficient [...]

A Simple, Accurate Capacitance-Voltage Model of Undoped Silicon Nanowire MOSFETs

Lin S., Zhou X., See G.H., Zhu G., Wei C., Zhang J., Chen Z., Nanyang Technological University, SG

Gate-All-Around (GAA), or surrounding-gate, MOSFET is one of the most promising structures beyond bulk CMOS. In this paper, we present a simple, accurate C-V model of undoped silicon nanowire MOSFETs. Different with other models, proposed [...]