Compact Modeling

MOSFET threshold voltage: definition, extraction, and applications

Machado M.B., Siebel O., Schneider M.C., Galup-Montoro C., Federal University of Santa Catarina, BR

The threshold voltage VT is a fundamental parameter in the characterization of MOS transistors and should be used, whatever is the adopted model for the transistor. The classical definition of threshold: phis = 2phiF +V [...]

Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type

Miura-Mattausch M., Miyake M., Kikuchihara H., Feldmann U., Amakawa S., Mattausch H.J., Miura-Mattausch M., Hiroshima University, JP

Many possible future device structures are investigated in parallel to obtain highest performance features. It has been shown that an SOI-MOSFET with a thin body enables both high device performances and suppression of statistical variations. [...]

Guidelines for Verilog-A Compact Model Coding

Depeyrot G., Poullet F., Dolphin Integration, FR

Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for both simulation and synthesis (IEEE1364-2001 and [...]

Modeling of Mismatch and Across-Chip Variations in Compact Device Models

Lu N., IBM, US

For analog circuit designers, both reducing device mismatch and having a good device mismatch model are very important. Pelgrom characterized device mismatch between two devices separated by a finite distance D as sqrt[a^2/(W*L) + b^2*D^2]. [...]

Improved Compact Model of Quantum Sub-band Energy Levels for MOSFET Device Application

Feldman W., Cumberbatch E., Abebe H., USC/ISI, US

Compact models for quantum mechanical behavior of transistors are becoming increasingly important as shrinking transistor sizes bring the oxide thickness to below four nanometers. An exponential approximation for the silicon potential is used to derive [...]

Compact Modeling of Signal Transients for Dispersionless Interconnects With Resistive, Capacitive and Inductive Terminal Loads

Liu Chi, Zhou Z., Lin X., Xia J., Zhang X., He J., Peking University, CN

In this paper, compact models for transient response of dispersionless interconnects are rigorously derived with resistive, inductive and capacitive terminal loads. The proposed compact models are verified by the HSPICE simulation with high accuracy and [...]

Bias Dependence of Low Frequency Noise in 90nm CMOS

Mavredakis N., Antonopoulos A., Bucher M., Technical University of Crete, GR

The bias dependence of low frequency noise (LFN) is investigated with measurements in 90nm CMOS. A recent charge-based LFN model combining carrier and mobility fluctuation components is compared to data from multi-finger devices with a [...]

Analytical model of quantum threshold voltage in short-channel nanowire MOSFET including band structure effects

Dura J., Martinie S., Munteanu D., Jaud M-A, Barraud S., Autran J-L, CEA/LETI/MINATEC, FR

The particular shape of Gate-All-Around (GAA) nanowires allows a much higher electrostatic control of the active region than conventional devices, as required for the integration at the end-of-roadmap. This architecture is suitable for ultra-scaled devices [...]

Analytical Solution of Surface Potential for Un-Doped Surrounding-Gate MOSFET

Dey A., DasGupta A., Arizona State University, US

Surrounding-Gate MOS transistors are seen as viable slternative to the problems of bulk MOSFET in deep sub-micron region. However modeling of drain current and capacitances, like other MOS structures require solution of an implicit equation. [...]