Interconnect – TechConnect Briefs

CarrICool – the Innovative 3D Interposer Platform for HPC Systems: Analysis, Simulations, Optimization, Practice for Reliability Improvement and Performance Increase

Janczyk G., Bieniek T., Bajurko P., Instytut Technologii Elektronowej, PL

This paper presents specific solutions being developed in frame of the CarrICool (abbr. “Modular Interposer System Architecture providing scalable Heat Removal, Power Delivery and Optical Signaling”) European FP7 project. The presented research and developed solutions [...]

Advanced Packaging for Next Generation Imaging and Sensor Devices

Kulick J., Indiana Integrated Circuits, LLC, US

Quilt Packaging is a unique and versatile edge-interconnect technology that utilizes “nodule” structures that extend out from the vertical facets along the edges of chips to allow for inter-chip communication. QP has demonstrated world-record chip-to-chip [...]

Field-Based 3D Capacitance Modeling for sub-45-nm On-Chip Interconnect

Zhang A., Zhao W., Ye Y., He J., Chen A., Chan M., Beijing University of Aeronautics and Astronautics, CN

Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes the electric field into various regions and gives solutions for each part. The total ground capacitance is the summation of all components. [...]

Compact Modeling of Signal Transients and Integrity Analysis for Dispersionless Interconnect

Zhao W., PKU HKUST Shenzhen Institution of IER., CN

In this paper, a compact model for transient response of the dispersionless interconnects is rigorously derived with resistive, inductive and capacitive load terminations. The proposed compact models are verified by the HSPICE simulation result to [...]

Compact Modeling of Signal Transients for Dispersionless Interconnects With Resistive, Capacitive and Inductive Terminal Loads

Liu Chi, Zhou Z., Lin X., Xia J., Zhang X., He J., Peking University, CN

In this paper, compact models for transient response of dispersionless interconnects are rigorously derived with resistive, inductive and capacitive terminal loads. The proposed compact models are verified by the HSPICE simulation with high accuracy and [...]

Castellated-Gate MOSFETs as Power Transistors for Nanometer CMOS and Post-CMOS Integrated Nanosystems

Seliskar J.J., HiperSem Inc., US

Analysis of the constant-voltage scaling characteristics of Fully-Depleted Castellated Gate (FDCG) MOSFETs reveals near term opportunities for these devices as the replacement for the “thick oxide” I/O device in CMOS System-On-A-Chip (SoC) technologies (e.g. the [...]

Airgap and Line Slope Modeling for Interconnect

Badrieh F., Puchner H., Cypress Semiconductor, US

We have devised a generic methodology for characterizing airgaps and line slope and including those features in interconnect modeling. The method is silicon-based and can be used to accurately model the impact on capacitance. Our [...]

Nano Scale Autonomous Error-Tolerant (AET) Cellular Network

Liu J., Weerasekera R., Zheng L-R, Tenhunen H., Royal Institute of Technology (KTH), SE

we propose a bottom-up approach using nano-CMOS hybrid Autonomous Error-Tolerant (AET) cellular network architecture. In our approach, each hexagonal AET cell consists of a nano-core dedicated for local computing, CMOS cell peripherals responsible for cell [...]

Three-Dimensional Transient Electro-Thermal Interconnect Simulation for Stress and Electromigration Analysis

Holzer S., Hollauer Ch., Ceric H., Wagner S., Entner R., Langer E., Grasser T., Selberherr S., Vienna University of Technology, AT

We introduce the combination of three-dimensional transient electro-thermal interconnect simulations for intrinsic thermo-mechanical stress problems. In order to study the development of thermal stresses we use a finite element simulator for the investigation on stresses [...]

Extraction of Coupled RLC Network from Multi-level Interconnects for Full Chip Simulation

Yoon S., Won T., Inha University, KR

In this paper, an approach is proposed for extracting coupled RLC network from multi-level interconnects. The proposed approach starts with a step of partitioning the layout of the full-chip under consideration into several sub-layouts, followed [...]