Extraction of Coupled RLC Network from Multi-level Interconnects for Full Chip Simulation

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In this paper, an approach is proposed for extracting coupled RLC network from multi-level interconnects. The proposed approach starts with a step of partitioning the layout of the full-chip under consideration into several sub-layouts, followed by steps of fracturing the partitioned layout and transforming into the three-dimensional structure. The layout is then classified into three species of segments, i.e. electrical node segments, resistive segments, capacitive segments, in order to generate a coupled RLC network from the layout data. These segments are employed for specifying the simulation domain and the boundary condition. Finally, the parasitics are calculated by a finite element method. A sampler circuit, which has 24 transistors for a 3.3V CMOS technology with 0.3mm feature size, was examined for the application of our approach. In this work, the number of nodes for FEM calculation was 68,115 with 375,624 tetrahedrons, and the required CPU time was approximately one hour on ULTRA SPARC 10 workstation.

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Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2002 International Conference on Modeling and Simulation of Microsystems
Published: April 22, 2002
Pages: 620 - 623
Industry sector: Sensors, MEMS, Electronics
Topic: Modeling & Simulation of Microsystems
ISBN: 0-9708275-7-1