Weerasekera R. – TechConnect Briefs

Nano Scale Autonomous Error-Tolerant (AET) Cellular Network

Liu J., Weerasekera R., Zheng L-R, Tenhunen H., Royal Institute of Technology (KTH), SE

we propose a bottom-up approach using nano-CMOS hybrid Autonomous Error-Tolerant (AET) cellular network architecture. In our approach, each hexagonal AET cell consists of a nano-core dedicated for local computing, CMOS cell peripherals responsible for cell [...]

A Nanocore/CMOS Hybrid System-on-Package (SoP) Architecture for Future Nanoelectronic Systems

Weerasekera R., Liu J., Zheng L-R, Tenhunen H., LECS/IMIT/KTH, SE

We propose Autonomous Error-Tolerant (AET) cellular network based architecture for future nano-electronic systems. Each AET cell consists of a nano-core, dedicated for local computing, CMOS cell-peripherals, responsible for cell I/O and System-level tasks, and their [...]