Miura-Mattausch M. – Page 3 – TechConnect Briefs

The Surface-Potential-Based model HiSIM-SOI and its Application to 1/f Noise in Fully-Depleted SOI-MOSFETs

Sadachika N., Yusoff M.Md., Uetsuji Y., Bhuyan M.H., Kitamaru D., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Weiss L., Feldmann U., Baba S., Graduate School of Advanced Sciences of Matter, Hiroshima University, JP

Fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation is developed. HiSIM-SOI solves surface potentials at all three SOI-surfaces along the depth direction self-consistently. Besides comparison to measured I-V characteristics, the model is verified with 1/f noise [...]

RF-MOSFET Model Parameter Extraction with HiSIM

Miura-Mattausch M., Sadachika N., Murakawa M., Mimura S., Higuchi T., Itoh K., Inagaki R., Iguchi Y., Hiroshima University, JP

This paper discusses a feasibility of an automatic parameter extraction method with the GA (Genetic Algorithm) for surface-potential-based MOSFET model HiSIM (Hiroshima-university STARC IGFET Model), where all device characteristics are described as functions of the [...]

Advanced Compact Models for MOSFETs

Watts J., McAndrew C., Enz C., Galup-Montoro C., Gildenblat G., Hu C., van Langevelde R., Miura-Mattausch M., Rios R., Sah C-T, Joint Paper, US

The combination of decreasing MOSFET dimensions and increasing use of MOSFETs for analog and RF application has created the need for advanced compact models for MOSFET circuit design. The first generation of MOSFET models rely [...]

Noise Modeling with HiSIM Based on Self-Consistent Surface-Potential Description

Miura-Mattausch M., Hosokawa S., Navarro D., Matsumoto S., Ueno H., Mattausch H.J., Miura-Mattausch M., Ohguro T., Iizuka T., Taguchi M., Kage T., Miyamoto S., Hiroshima University, JP

Accurate prediction of noise characteristics is a prerequisite for RF-circuit simulation. We demonstrate here that the 1/f noise is modeled only with the trap density as a model parameter and the thermal drain noise is [...]

Gate Current Partitioning in MOSFET Models for Circuit Simulation

Ngo Q., Navarro D., Mizoguchi T., Hosakawa S., Ueno H., Miura-Mattausch M., Yang C.Y., Santa Clara University, US

Gate current plays a critical role in circuits featuring sub-100nm MOSFETs. This paper elucidates the importance of gate current partitioning for accurate circuit simulation. Past publications have presented gate current models based on surface potential [...]

HiSIM: Accurate Charge Modeling Important for RF Era

Miura-Mattausch M., Navarro D., Ueno H., Mattausch H.J., Miura-Mattausch M., Morikawa K., Itoh S., Kobayashi A., Masuda H., Hiroshima University, JP

Extension of the gradual-channel approximation is presented with the surface-potential-based MOSFET modeling. All phenomena observed under the saturation condition are described by the potential increase in the pinch-off region in a self-consistent way. The charge [...]

HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies

Miura-Mattausch M., Ueno H., Mattausch J.H., Miura-Mattausch M., Kumashiro S., Yamaguchi T., Yamashita K., Nakayama N., Hiroshima University, JP

Surface-potential-basedMOSFET modeling is shown to be the right direction. Model parameters reflect the physical device parameters of advanced technologies directly, and can therefore be even scalable with technology changes. These advantages are demonstrated with HiSIM, [...]