Sadachika N., Yusoff M.Md., Uetsuji Y., Bhuyan M.H., Kitamaru D., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Weiss L., Feldmann U., Baba S.
Graduate School of Advanced Sciences of Matter, Hiroshima University, JP
Fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation is developed. HiSIM-SOI solves surface potentials at all three SOI-surfaces along the depth direction self-consistently. Besides comparison to measured I-V characteristics, the model is verified with 1/f noise analysis, sensitive to the carrier concentration and distribution along the channel. The carrier concentration increase of SOI-MOSFET results in enhanced 1/f noise in comparison with the bulk-MOSFET. Our results predict that further reduction of the silicon-layer thickness for achieving higher driving capability will cause unavoidable enhancement of the noise.
Journal: TechConnect Briefs
Volume: Technical Proceedings of the 2005 Workshop on Compact Modeling
Published: May 8, 2005
Pages: 155 - 158
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Nanoparticle Synthesis & Applications