Chiah S.B. – TechConnect Briefs

Hybrid Process Design Kit: Single-Chip Monolithic III-V/Si Cascode GaN-HEMT

Chiah S.B., Zhou X., Lee K.E.K., Antoniadis D., Nanyang Technological University, SG

In this paper, we present the design of a cascode GaN-HEMT (CGH) structure in the monolithic integration of III-V/Si fabrication platform to fabricate monolithic III-V/Si CGH structures on a single chip by using hybrid process [...]

A Hybrid Process Design Kit: Towards Integrating CMOS and III-V Devices

Chiah S.B., Zhou X., Lee K.E.K., Ng C.Y., Antoniadis D., Fitzgerald E.A., Nanyang Technological University, SG

A hybrid process design kit (PDK) for novel integrated circuits incorporating high performance compound semiconductor materials and devices into existing production Si-CMOS compatible foundry process is presented. The hybrid PDK permits direct integration of Au-free [...]

Compact Model Characteristics for Generic MIS-HEMTs

Zhou H.T., Zhou X., Chiah S.B., Syamal B., Zhou H.T., Zhou X., Ajaykumar A., Liu X., Nanyang Technological University, SG

III-V channel field-effect transistors (FETs), such as metal–insulator–semiconductor high electron-mobility transistors (MIS-HEMTs), have emerged as promising candidates for future generation high-frequency, high-voltage, and high-power applications. Development of a compact model for generic HEMTs in III-V/Si [...]

Unified Regional Approach to High Temperature SOI DC/AC Modeling

Chiah S.B., Zhou X., Chen H-M, Chen Z., Chen H-M, Chen Z., Nanyang Technological University, SG

This paper extends the recent model development [1] to include temperature effect in a range from room temperature to 300C. The extraction of the temperature coefficients used in the model and the prediction of the [...]

A Simplified Model for Dynamic Depletion in Doped UTB-SOI/DG-FinFETs

Zhou X., Chiah S.B., Nanyang Technological University, SG

Compact modeling for doped-body MOSFETs, such as ultra-thin body (UTB) SOI and double-gate (DG) FinFETs, represents the most challenging task since it involves the Poisson’s solution with two boundary conditions, which is not available when [...]

Gummel Symmetry with Higher-order Derivatives in MOSFET Compact Models

See G.H., Zhou X., Chandrasekaran K., Chiah S.B., Zhu G.J., Zhu Z.M., Lim G.H., Wei C.Q., Lin S-H, Zhu G.J., Zhu Z.M., Nanyang Technological University, SG

One of the critical problems in Gummel symmetry at higher-order derivatives that still exists in current and next generation MOS compact models has been solved with a simple modification of the mathematical smoothing function. The [...]

Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach

Chandrasekaran K., Zhu Z.M., Zhou X., Shangguan W., See G.H., Chiah S.B., Rustagi S.C., Singh N., Nanyang Technological University, SG

A compact model for the explicit surface potential equation of doped symmetric double-gate MOSFET from Poisson equation with regional approach is presented. It’s scalable for all doping and channel thicknesses and has been proved to [...]

Scalable MOSFET Short-channel Charge Model in All Regions

See G.H., Chiah S.B., Zhou X., Chandrasekaran K., Shangguan W., Zhu Z., Lim G.H., Pandey S.M., Cheng M., Chu S., Hsia L.-C., NTU, SG

Short-channel effects (SCEs) for both intrinsic chargesand extrinsic capacitances need to be modeled when theMOSFET channel is short. The intrinsic SCEs are modeled using bulk-charge sharing and quasi-two dimensional potential barrier loweirng; extrinsic overlap capacitances [...]

Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling

Zhou X., Chandrasekaran K., Chiah S.B., Shangguan W., Zhu Z., See G.H., Mani Pandey S., Lim G.H., Rustagi S., Cheng M., Chu S., Hsia L.-C., Nanyang Technological University, SG

In this paper, we extend our unified regional approach to bulk-MOS charge modeling with non-pinned surface potential for various device structures such as PD/FD/UTB SOI and s-DG MOSFETs, including strained-Si channel. The regional solutions make [...]

A Technology-based Compact Model for Predictive Deep-Submicron MOSFET Modeling and Characterization

Zhou X., Chiah S.B., Lim K.Y., Nanyang Technological University, SG

This paper presents new development results of our compact model (Xsim) for deep-submicron MOSFETs. Although a threshold-voltage-based and source-referenced regional model, Xsim meets the basic requirements of continuity (to third-order derivatives), scalability (entire geometry range), [...]