Hybrid Process Design Kit: Single-Chip Monolithic III-V/Si Cascode GaN-HEMT

, , , , ,

Keywords: , , , , , ,

In this paper, we present the design of a cascode GaN-HEMT (CGH) structure in the monolithic integration of III-V/Si fabrication platform to fabricate monolithic III-V/Si CGH structures on a single chip by using hybrid process design kit (h-PDK). The design of the monolithic CGH structure uses low voltage Si-based MOSFET and high voltage D-mode GaN-HEMT that are offered in the in-house developed h-PDK. The h-PDK provides a complete platform in designing a monolithic CGH circuit that includes hybrid (III-V/Si devices) circuit simulation and layout verification under commercial EDA toolset. It is used to generate GDS-II file for a tape-out submission. The tape-out of the monolithic CGH structures on 8-inch multi-purpose wafers (MPW) has been submitted for fabrication. The designs for the tape-out include geometric variation of GaN-HEMT devices, such as the length of the drain-diffusion region to enhance the breakdown voltage and the multi-finger CGH structures on a single die for high power applications.

PDF of paper:

Journal: TechConnect Briefs
Volume: 4, Informatics, Electronics and Microsystems: TechConnect Briefs 2018
Published: May 13, 2018
Pages: 257 - 260
Industry sector: Sensors, MEMS, Electronics
Topics: WCM - Compact Modeling
ISBN: 978-0-9988782-1-8