TechConnect Proceedings Papers
Month: June 2011
Process Variability Modeling for VLSI Circuit Simulation
It is well known that the process variability has severely impacted the delay and power variability in VLSI devices, circuits, and chips, and the impact of process variability keeps increasing as MOSFET devices and CMOS [...]
Modeling of High Voltage Devices for ESD Event Simulation
BCDMOS process technologies are key in enabling highly integrated mixed-signal application for the automotive, medical and industrial sectors. Achieving satisfactory ESD performance in high voltage mixed-signal applications requires synthesized co-design using circuit-level ESD event simulation [...]
High-Voltage MOSFET Compact Modeling
In many new applications like communication and automotive electronics the usage of integrated high voltage MOS transistors (LDMOS and DMOS) requires highly accurate compact models. At first we discuss the industrial requirements for modern high [...]
A Fully Anlytical Model for Carbon Nanotube FETs including Quantum Capacitances and Electrostatics
In this paper, an analytical model of intrinsic carbon nanotube field effect transistors (CNFETs) is presented based on ballistic transport and careful analysis of the quantum capacitances, which requires neither iteration nor numeric integration. Essential [...]
Compact Subthreshold Modeling of Rectangular Gate and Trigate MOSFETs
We have previously shown that the subthreshold potential distribution of DG and circular gate MOSFETs can be precisely modeled using conformal mapping techniques. Simpler, unified models suitable for circuit design can also be established for [...]
Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA MOSFETs
This paper presents a unified compact model (Xsim) for bulk/SOI MOSFETs, double-gate (DG) FinFETs, and gate-all-around (GAA) silicon-nanowires (SiNWs) that has been under development over the past 13 years. One key feature of the model [...]
Compact Models for sub-22nm MOSFETs
Chauhan Y.S., Lu D., Venugopalan S., Morshed T., Karim M.A., Niknejad A., Hu C., University of California-Berkeley, US
FinFET and UTBSOI FET (or ETSOI) are the two promising multi-gate FET candidates for sub-22nm CMOS technology. BSIM multi-gate FET models (BSIM-CMG and BSIM-IMG) are the surface potential based physical compact models for FinFET and [...]
UF “Compact” Models: A Historical Perspective
The history of the developments of “compact” models for SOI MOSFETs at the University of Florida (UF) is reviewed. The uniqueness and innovation of the UF “process-based” models are reiterated, and their global utility as [...]
MOSFET threshold voltage: definition, extraction, and applications
The threshold voltage VT is a fundamental parameter in the characterization of MOS transistors and should be used, whatever is the adopted model for the transistor. The classical definition of threshold: phis = 2phiF +V [...]