Papers – Page 16 – TechConnect Briefs

RF Applications of MOS Model 11

van Langevelde R., Scholten A.J., Tiemeijer L.F., Havens R.J., Klaassen D.B.M., Philips Research Laboratories, NL

RF-CMOS applications impose increasingly stringent requirements on compact models used in circuit simulation. In this paper several of these issues will be addressed together with a discussion of the state-of-the-art of compact modelling.

The EKV 3.0 Compact MOS Transistor Model: Accounting for Deep-Submicron Aspects

Bucher M., Enz C., Krummenacher F., Sallese J.M., Lallement C., Porret A.S., National Technical University of Athens, GR

The EKV 3.0 compact MOS transistor model for advanced IC design is presented. Its basis is an ideal analytical charge-based model including static to non-quasistatic dynamic aspects and noise. The ideal model is extended to [...]

The Foundations of the EKV MOS Transistor Charge-Based Model

Enz C., Bucher M., Porret A.S., Sallese J.M., Krummenacher F., Swiss Center for Electronics and Microtechnology, CH

This paper presents the foundations that lead to the EKV MOS transistor compact model. It describes all the basic concepts required to derive the large-signal and smallsignal charge-based model that is valid in all modes [...]

Engineering BSIM for the Nano-Technology Era and Beyond

Chan M., Hu C., Hong Kong University of Science and Technology, HK

This paper presents the current status of the forth generation BSIM model and issues of modeling CMOS based devices with nanometer dimensions. Due to the divergence of device structures in sub-0.1 m gate length, it [...]

Overview of An Advanced Surface-Potential-Based MOSFET Model (SP)

Gildenblat G., Chen T.L., Pennsylvania State University, US

This paper outlines a new surface-potential-based compact MOSFET model (SP) developed at The Pennsylvania State University. The main objective of this work is to find practical engineering solutions of several long-standing problems of surface-potential-based modeling [...]

Standardization and Validation of Compact Models

Brooks B., Green K., Krick J., Vrotsos T., Weiser D., Texas Instruments, US

The idea of standardizing compact (SPICE-like) models has recently gained momentum in the semiconductor industry. However, since compact model equations reside in software, the concept of standardization is difficult. Several key issues must be addressed, [...]

Detailed Comparison of the SP2001, EKV, and BSIM3 Models

Bendix P., LSI Logic, US

Practical comparisons are made of three available or soon to be available compact MOS models----SP2001 (surface potential 2001), EKV, and BSIM3. They are compared both in their DC and AC quality of fits to measured [...]

Challenges of Modeling VLSI Interconnects in the DSM Era

Arora N.D., Simplex Solutions, US

As VLSI technology shrinks to deep sub-micron (DSM) geometries (below 0.18mm), the parasitic due to interconnects are becoming a limiting factor in determining circuit performance. An accurate modeling of interconnect parasitic resistance (R), capacitance (C) [...]

The New Approach to the Power Semiconductor Devices Modelling

Starzak L., Zubert M., Napieralski A., Technical University of Lodz, PL

Due to their specific structures the power devices need special models different from those developed for low power electronics. The development of such special models is far from being simple as distributed nature of phenomena [...]

Novel Computing Architecture on Arrays of Josephson Persistent Current Bits

Han J., Jonker P., Delft University of Technology, NL

A superconducting qubit (or quantum bit), which consists of a micrometer-sized loop with three Josephson junctions, has two persistent currents of opposite direction as its two states. The states of the qubit can be brought [...]