Papers – Page 17 – TechConnect Briefs

Characterization of “Multipath Interconnects” for Microelectronic and Nanotechnology Circuits

Goel A.K., Eady N.R., Michigan Technological University, US

A multipath interconnect carries a signal by using the concept of parallel processing by providing two or more paths between the driver and the load. These paths are stacked vertically isolated from one another by [...]

Compact Modeling of Tunneling Breakdown in PN Junctions for Computer-Aided ESD Design (CAD for ESD)

Subramanian Y., Darling R.B., University of Washington, US

This paper presents compact, physically-based electrothermal models for direct as well as indirect bandgap tunneling processes in pn-junctions for use in network simulators (e.g. Saber or VHDL-A). The model for indirect tunneling has been validated [...]

Simulation of Heterojunction Bipolar Transistor with Domain Decomposition Method

Zhang Y., Ruden P.P., Oklahoma State University, US

Domain decomposition method is used in simulation of the band profile and the majority carrier concentration profile of AlGaN/GaN heterojunction bipolar transistors. The method is very stable and efficient. With this method different device structures [...]

Extraction of Coupled RLC Network from Multi-level Interconnects for Full Chip Simulation

Yoon S., Won T., Inha University, KR

In this paper, an approach is proposed for extracting coupled RLC network from multi-level interconnects. The proposed approach starts with a step of partitioning the layout of the full-chip under consideration into several sub-layouts, followed [...]

Physics-Based and Compact Models for Self-Heating in High-Speed Bipolar Integrated Circuits

Pacelli A., Palestri P., Mastrapasqua M., State University of New York-Stony Brook, US

We present three-dimensional heat-transport simulation for bipolar transistors. The simulations are validated on experimental data, and are employed to develop analytical models for the thermal resistance of devices fabricated on bulk and SOI substrate, and [...]

An Algorithm for the Inclusion of RC Compact Models of Packages into Board Level Thermal Simulation Tools

Rencz M., Székely V., Courtois B., TIMA-CMP, FR

The paper presents an algorithm for the co-simulation of packages, given with the RC compact models, and the printed circuit boards. This enables beyond the correct detailed consideration of the heat transfer in the board [...]

Compact Thermal Model for Transient Temperature Fields in Electronic Systems

Gerstenmaier Y.C., Wachutka G., Münich University of Technology, DE

A thermal model is presented, which describes the evolution of the temperature distribution in electronic systems. Introducing a set of deliberately chosen effective time constants, the time dependence is given by convolution integrals with the [...]

A Comprehensive Modeling of MOS Transistors in a 0.35um Technology for Analog and Digital Applications

Keshavarz A., Khare P., Sampson R., STMicroelectronics, US

The purpose of this work is to present a comprehensive report of the MOS transistor characteristics in a 0.35um technology, both types being surface devices. Results include extensive geometrical and temperature dependencies of the most [...]

Capacitance-Voltage Characteristics of Metal-Oxide-Strained Semiconductor Si/SiGe Heterostructures

Cavassilas N., Autran J-L, CNRS, FR

We present theoretical investigation of mechanical strain-induced effects in metal-oxide-semiconductor (MOS) structures from an electrical point-of-view. In this work, we start by calculating the strained semiconductor band-structure using a k.p approach over the complete Brillouin [...]

Study of Electron Transport in SOI MOSFETs using Monte Carlo Technique with Full-Band Modeling

Takeda H., Mori N., Hamaguchi C., Osaka University, JP

In SOI MOSFETs, electrons are quantized into two-dimensional electron gas by the strong electric field normal to the interface. When the Si-layer thickness is thinner than the inversion layer width, the confinement becomes stronger and [...]